Re: [RFC PATCH 0/5] RFC for Zynq QSPI

From: Boris Brezillon <boris.brezillon@bootlin.com>
To: naga suresh kumar <nagasureshkumarrelli@gmail.com>
Cc: nagasure@xilinx.com, cyrille.pitchen@wedev4u.fr,
	marek.vasut@gmail.com, dwmw2@infradead.org,
	computersforpeace@gmail.com, boris.brezillon@free-electrons.com,
	linux-mtd@lists.infradead.org
Subject: Re: [RFC PATCH 0/5] RFC for Zynq QSPI
Date: Mon, 17 Sep 2018 17:05:22 +0200	[thread overview]
Message-ID: <20180917170522.0312ae8c@bbrezillon> (raw)
In-Reply-To: <CALgLF9K=rZxVx_QXvV_LH3OhidTcguZ=K=p=Lf9AfFbk4H+8Zw@mail.gmail.com>

Hi Naga,

On Mon, 17 Sep 2018 16:08:26 +0530
naga suresh kumar <nagasureshkumarrelli@gmail.com> wrote:

> Hi all,
> 
> Can i write the Zynq QSPI driver under the new spi/mem framework?

Yes, you should.

> As i said, it needs tweaking the mtd->size and spi read/write addresses.

Can you elaborate a bit on why you think this is needed? Did you look
at [1]? Maybe it will prevent us from exposing the flash size at the
spi-mem level.

> Can somebody share your thoughts on this(Adding Zynq QSPI Dual parallel and
> stacked)?

I always have a hard time with this naming. I guess stacked is when you
have 2 chips sharing the same I/O bus, and parallel is when you have 2
chips with one taking all of the I/O and the other taking the other
half. Is that correct?

If it is, then stacked mode should be easy to support (it's just a
matter of patching the spi layer to allow passing several CS lines to a
single device (in case of DT parsing, it means reg = <0 1> implies CS 0
and 1 are assigned to the same device. For the parallel, I don't have a
solution yet.

Anyway, I'd suggest that you start with something simple (a spi-mem
driver supporting ->exec_op() in Single/Dual/Quad mode), and build on
top of that for the advanced features you're mentioning here.

Regards,

Boris

[1]http://lists.infradead.org/pipermail/linux-mtd/2018-June/081460.html