From: Naga Sureshkumar Relli <nagasure@xilinx.com>
To: Marek Vasut <marek.vasut@gmail.com>,
"cyrille.pitchen@wedev4u.fr" <cyrille.pitchen@wedev4u.fr>,
"dwmw2@infradead.org" <dwmw2@infradead.org>,
"computersforpeace@gmail.com" <computersforpeace@gmail.com>,
"boris.brezillon@free-electrons.com"
<boris.brezillon@free-electrons.com>
Cc: "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>
Subject: RE: [RFC PATCH 0/5] RFC for Zynq QSPI
Date: Fri, 23 Mar 2018 13:39:04 +0000 [thread overview]
Message-ID: <BY2PR02MB1411AE2E99CF723E42A2D1E9AFA80@BY2PR02MB1411.namprd02.prod.outlook.com> (raw)
In-Reply-To: <c06c5256-119d-ef90-0bf8-cdbc1720a7b9@gmail.com>
Hi Marek,
Thanks for reviewing the patch.
> -----Original Message-----
> From: Marek Vasut [mailto:marek.vasut@gmail.com]
> Sent: Friday, March 23, 2018 6:22 PM
> To: Naga Sureshkumar Relli <nagasure@xilinx.com>;
> cyrille.pitchen@wedev4u.fr; dwmw2@infradead.org;
> computersforpeace@gmail.com; boris.brezillon@free-electrons.com
> Cc: linux-mtd@lists.infradead.org; Naga Sureshkumar Relli
> <nagasure@xilinx.com>
> Subject: Re: [RFC PATCH 0/5] RFC for Zynq QSPI
>
> On 03/23/2018 01:21 PM, Naga Sureshkumar Relli wrote:
> > Xilinx Zynq uses a QSPI controller that is based on the Cadence SPI IP.
>
> Don't we have a CQSPI driver already ? Why is this adding a new one ?
Zynq QSPI Controller is designed by using Cadence SPI IP core in order to add multi bit IO capability.
The modified core is Zynq QSPI Controller core. Both are different.
>
> --
> Best regards,
> Marek Vasut
Thanks,
Naga Sureshkumar Relli.
next prev parent reply other threads:[~2018-03-23 13:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-23 12:21 [RFC PATCH 0/5] RFC for Zynq QSPI Naga Sureshkumar Relli
2018-03-23 12:21 ` [RFC PATCH 1/5] spi: Add support for Zynq qspi controller Naga Sureshkumar Relli
2018-03-23 12:21 ` [RFC PATCH 2/5] mtd: spi-nor: Add support for Zynq QSPI controller Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 3/5] mtd: spi-nor: Add Dual Parallel and Stacked support for Zynq QSPI Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 4/5] spi: Add PM Support for Zynq QSPI controller Naga Sureshkumar Relli
2018-03-23 12:22 ` [RFC PATCH 5/5] devicetree: Add devicetree bindings documentation for Naga Sureshkumar Relli
2018-03-23 14:47 ` Miquel Raynal
2018-03-23 12:52 ` [RFC PATCH 0/5] RFC for Zynq QSPI Marek Vasut
2018-03-23 13:39 ` Naga Sureshkumar Relli [this message]
2018-04-16 7:25 ` Naga Sureshkumar Relli
[not found] ` <CALgLF9K=rZxVx_QXvV_LH3OhidTcguZ=K=p=Lf9AfFbk4H+8Zw@mail.gmail.com>
2018-09-17 15:05 ` Boris Brezillon
2018-09-17 15:07 ` Boris Brezillon
[not found] ` <CALgLF9JVweEcEm6L33HaHp4HtXhmsZL7J5FDe8+O11i0Q1nukg@mail.gmail.com>
2018-09-18 7:17 ` Boris Brezillon
2018-09-18 8:58 ` Naga Sureshkumar Relli
2019-06-26 9:53 ` naga suresh kumar
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