* [PATCH] spi-nor: intel-spi: Whitelist 4B read commands
@ 2019-07-12 12:14 Sverdlin, Alexander (Nokia - DE/Ulm)
2019-08-20 15:24 ` Tudor.Ambarus
2019-08-21 8:19 ` Tudor.Ambarus
0 siblings, 2 replies; 4+ messages in thread
From: Sverdlin, Alexander (Nokia - DE/Ulm) @ 2019-07-12 12:14 UTC (permalink / raw)
To: linux-mtd
Cc: Vignesh Raghavendra, Tudor Ambarus, Richard Weinberger,
Marek Vasut, Sverdlin, Alexander (Nokia - DE/Ulm),
Miquel Raynal, Brian Norris, David Woodhouse
From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
Flash chips up to 64Mbytes.
D-1500 Integrated PCH documenation however has inconsistencies regarding
FADDR register width and says nothing about particular commands issued
to support 64Mbytes of Flash.
Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
read operations work just fine after SPINOR_OP_READ_4B and
SPINOR_OP_READ_FAST_4B are white-listed (currently only
SPINOR_OP_READ_FAST_4B is used and only for Macronix).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
---
drivers/mtd/spi-nor/intel-spi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
index 1ccf23f..43e55a2e 100644
--- a/drivers/mtd/spi-nor/intel-spi.c
+++ b/drivers/mtd/spi-nor/intel-spi.c
@@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
switch (nor->read_opcode) {
case SPINOR_OP_READ:
case SPINOR_OP_READ_FAST:
+ case SPINOR_OP_READ_4B:
+ case SPINOR_OP_READ_FAST_4B:
break;
default:
return -EINVAL;
--
2.4.6
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] spi-nor: intel-spi: Whitelist 4B read commands
2019-07-12 12:14 [PATCH] spi-nor: intel-spi: Whitelist 4B read commands Sverdlin, Alexander (Nokia - DE/Ulm)
@ 2019-08-20 15:24 ` Tudor.Ambarus
2019-08-21 7:34 ` Mika Westerberg
2019-08-21 8:19 ` Tudor.Ambarus
1 sibling, 1 reply; 4+ messages in thread
From: Tudor.Ambarus @ 2019-08-20 15:24 UTC (permalink / raw)
To: alexander.sverdlin, linux-mtd, mika.westerberg
Cc: vigneshr, richard, marek.vasut, miquel.raynal, computersforpeace, dwmw2
Mika,
Would you please review the patch from below?
Thanks,
ta
On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote:
> External E-Mail
>
>
> From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
>
> spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
> Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
> Flash chips up to 64Mbytes.
> D-1500 Integrated PCH documenation however has inconsistencies regarding
> FADDR register width and says nothing about particular commands issued
> to support 64Mbytes of Flash.
>
> Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
> Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
> read operations work just fine after SPINOR_OP_READ_4B and
> SPINOR_OP_READ_FAST_4B are white-listed (currently only
> SPINOR_OP_READ_FAST_4B is used and only for Macronix).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
> ---
> drivers/mtd/spi-nor/intel-spi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
> index 1ccf23f..43e55a2e 100644
> --- a/drivers/mtd/spi-nor/intel-spi.c
> +++ b/drivers/mtd/spi-nor/intel-spi.c
> @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
> switch (nor->read_opcode) {
> case SPINOR_OP_READ:
> case SPINOR_OP_READ_FAST:
> + case SPINOR_OP_READ_4B:
> + case SPINOR_OP_READ_FAST_4B:
> break;
> default:
> return -EINVAL;
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] spi-nor: intel-spi: Whitelist 4B read commands
2019-08-20 15:24 ` Tudor.Ambarus
@ 2019-08-21 7:34 ` Mika Westerberg
0 siblings, 0 replies; 4+ messages in thread
From: Mika Westerberg @ 2019-08-21 7:34 UTC (permalink / raw)
To: Tudor.Ambarus
Cc: vigneshr, richard, marek.vasut, linux-mtd, miquel.raynal,
alexander.sverdlin, computersforpeace, dwmw2
On Tue, Aug 20, 2019 at 03:24:37PM +0000, Tudor.Ambarus@microchip.com wrote:
> Mika,
>
> Would you please review the patch from below?
Sure.
>
> Thanks,
> ta
>
> On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote:
> > External E-Mail
> >
> >
> > From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
> >
> > spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
> > Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
> > Flash chips up to 64Mbytes.
> > D-1500 Integrated PCH documenation however has inconsistencies regarding
> > FADDR register width and says nothing about particular commands issued
> > to support 64Mbytes of Flash.
Unfortunately I don't have any additional documentation that could help.
> > Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
> > Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
> > read operations work just fine after SPINOR_OP_READ_4B and
> > SPINOR_OP_READ_FAST_4B are white-listed (currently only
> > SPINOR_OP_READ_FAST_4B is used and only for Macronix).
If it works in your testing I don't see why we would not support them
especially since these are just reads.
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
The patch itself is trivial enough and looks fine to me.
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> > ---
> > drivers/mtd/spi-nor/intel-spi.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
> > index 1ccf23f..43e55a2e 100644
> > --- a/drivers/mtd/spi-nor/intel-spi.c
> > +++ b/drivers/mtd/spi-nor/intel-spi.c
> > @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
> > switch (nor->read_opcode) {
> > case SPINOR_OP_READ:
> > case SPINOR_OP_READ_FAST:
> > + case SPINOR_OP_READ_4B:
> > + case SPINOR_OP_READ_FAST_4B:
> > break;
> > default:
> > return -EINVAL;
> >
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] spi-nor: intel-spi: Whitelist 4B read commands
2019-07-12 12:14 [PATCH] spi-nor: intel-spi: Whitelist 4B read commands Sverdlin, Alexander (Nokia - DE/Ulm)
2019-08-20 15:24 ` Tudor.Ambarus
@ 2019-08-21 8:19 ` Tudor.Ambarus
1 sibling, 0 replies; 4+ messages in thread
From: Tudor.Ambarus @ 2019-08-21 8:19 UTC (permalink / raw)
To: alexander.sverdlin, linux-mtd
Cc: vigneshr, richard, marek.vasut, miquel.raynal, computersforpeace, dwmw2
On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote:
> External E-Mail
>
>
> From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
>
> spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
> Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
> Flash chips up to 64Mbytes.
> D-1500 Integrated PCH documenation however has inconsistencies regarding
> FADDR register width and says nothing about particular commands issued
> to support 64Mbytes of Flash.
>
> Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
> Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
> read operations work just fine after SPINOR_OP_READ_4B and
> SPINOR_OP_READ_FAST_4B are white-listed (currently only
> SPINOR_OP_READ_FAST_4B is used and only for Macronix).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
> ---
> drivers/mtd/spi-nor/intel-spi.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git,
spi-nor/next branch.
Thanks,
ta
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-08-21 8:20 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-12 12:14 [PATCH] spi-nor: intel-spi: Whitelist 4B read commands Sverdlin, Alexander (Nokia - DE/Ulm)
2019-08-20 15:24 ` Tudor.Ambarus
2019-08-21 7:34 ` Mika Westerberg
2019-08-21 8:19 ` Tudor.Ambarus
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).