* [PATCH v5 1/5] mtd: spi-nor: rename SR_TB to indicate the bit used
[not found] <CGME20190821051626epcas1p4846ddc2378df756efaba78ed3a0a6057@epcas1p4.samsung.com>
@ 2019-08-21 5:15 ` Jungseung Lee
[not found] ` <CGME20190821051637epcas1p48d70755f6a16f04c3af59e73945b4674@epcas1p4.samsung.com>
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Jungseung Lee @ 2019-08-21 5:15 UTC (permalink / raw)
To: Marek Vasut, Tudor Ambarus, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, u.kleine-koenig, linux-mtd,
js07.lee, js07.lee
Each vendor uses different bits for SR_TB of flash.
To avoid ambiguity, rename SR_TB to indicate the bit used.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
v5:
- remake patch based on latest spi-nor/next tree
drivers/mtd/spi-nor/spi-nor.c | 10 +++++-----
include/linux/mtd/spi-nor.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3790830d0d99..587f23480e5d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1421,7 +1421,7 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
} else {
pow = ((sr & mask) ^ mask) >> shift;
*len = mtd->size >> pow;
- if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB_BIT5)
*ofs = 0;
else
*ofs = mtd->size - *len;
@@ -1551,13 +1551,13 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if (!(val & mask))
return -EINVAL;
- status_new = (status_old & ~mask & ~SR_TB) | val;
+ status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
/* Disallow further writes if WP pin is asserted */
status_new |= SR_SRWD;
if (!use_top)
- status_new |= SR_TB;
+ status_new |= SR_TB_BIT5;
/* Don't bother if they're the same */
if (status_new == status_old)
@@ -1633,14 +1633,14 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
return -EINVAL;
}
- status_new = (status_old & ~mask & ~SR_TB) | val;
+ status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
/* Don't protect status register if we're fully unlocked */
if (lock_len == 0)
status_new &= ~SR_SRWD;
if (!use_top)
- status_new |= SR_TB;
+ status_new |= SR_TB_BIT5;
/* Don't bother if they're the same */
if (status_new == status_old)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 63560b375168..66c891f0d328 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -127,7 +127,7 @@
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
-#define SR_TB BIT(5) /* Top/Bottom protect */
+#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
#define SR_SRWD BIT(7) /* SR write protect */
/* Spansion/Cypress specific status bits */
#define SR_E_ERR BIT(5)
--
2.17.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 2/5] mtd: spi-nor: Fix wrong TB selection on winbond/gigadevice flashes
[not found] ` <CGME20190821051637epcas1p48d70755f6a16f04c3af59e73945b4674@epcas1p4.samsung.com>
@ 2019-08-21 5:15 ` Jungseung Lee
0 siblings, 0 replies; 5+ messages in thread
From: Jungseung Lee @ 2019-08-21 5:15 UTC (permalink / raw)
To: Marek Vasut, Tudor Ambarus, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, u.kleine-koenig, linux-mtd,
js07.lee, js07.lee
For winbond and gigadevice flashes, wrong bit for top/bottom selection
are being used. Fix it to use appropriate value.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
v5:
- remake patch based on latest spi-nor/next tree
drivers/mtd/spi-nor/spi-nor.c | 24 +++++++++++++++++++-----
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 587f23480e5d..5bed03e61bd0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1411,9 +1411,14 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
{
struct mtd_info *mtd = &nor->mtd;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 mask_tb = SR_TB_BIT5;
int shift = ffs(mask) - 1;
int pow;
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ mask_tb = SR_TB_BIT6;
+
if (!(sr & mask)) {
/* No protection */
*ofs = 0;
@@ -1421,7 +1426,7 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
} else {
pow = ((sr & mask) ^ mask) >> shift;
*len = mtd->size >> pow;
- if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB_BIT5)
+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & mask_tb)
*ofs = 0;
else
*ofs = mtd->size - *len;
@@ -1500,6 +1505,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 mask_tb = SR_TB_BIT5;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
@@ -1534,6 +1540,10 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
else
lock_len = ofs + len;
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ mask_tb = SR_TB_BIT6;
+
/*
* Need smallest pow such that:
*
@@ -1551,13 +1561,13 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if (!(val & mask))
return -EINVAL;
- status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
+ status_new = (status_old & ~mask & ~mask_tb) | val;
/* Disallow further writes if WP pin is asserted */
status_new |= SR_SRWD;
if (!use_top)
- status_new |= SR_TB_BIT5;
+ status_new |= mask_tb;
/* Don't bother if they're the same */
if (status_new == status_old)
@@ -1580,6 +1590,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 mask_tb = SR_TB_BIT5;
u8 shift = ffs(mask) - 1, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
@@ -1614,6 +1625,9 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
else
lock_len = ofs;
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ mask_tb = SR_TB_BIT6;
/*
* Need largest pow such that:
*
@@ -1633,14 +1647,14 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
return -EINVAL;
}
- status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
+ status_new = (status_old & ~mask & ~mask_tb) | val;
/* Don't protect status register if we're fully unlocked */
if (lock_len == 0)
status_new &= ~SR_SRWD;
if (!use_top)
- status_new |= SR_TB_BIT5;
+ status_new |= mask_tb;
/* Don't bother if they're the same */
if (status_new == status_old)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 66c891f0d328..654992a829bd 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -128,6 +128,7 @@
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
+#define SR_TB_BIT6 BIT(6) /* Top/Bottom protect (on Winbond/GigaDevice) */
#define SR_SRWD BIT(7) /* SR write protect */
/* Spansion/Cypress specific status bits */
#define SR_E_ERR BIT(5)
--
2.17.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 3/5] mtd: spi-nor: introduce SR_BP_SHIFT define
[not found] ` <CGME20190821051637epcas1p3e70e5142c92c2eebb9a9188779217b78@epcas1p3.samsung.com>
@ 2019-08-21 5:15 ` Jungseung Lee
0 siblings, 0 replies; 5+ messages in thread
From: Jungseung Lee @ 2019-08-21 5:15 UTC (permalink / raw)
To: Marek Vasut, Tudor Ambarus, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, u.kleine-koenig, linux-mtd,
js07.lee, js07.lee
The shift variable of SR_BP is conclusive because the first bit of SR_BP
is fixed on known flashes.
Introduce SR_BP_SHIFT define, and let them used by stm_* functions
to replace ffs operation to get shift value.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
v5:
- remake patch based on latest spi-nor/next tree
- Fix commit log
drivers/mtd/spi-nor/spi-nor.c | 11 +++++------
include/linux/mtd/spi-nor.h | 2 ++
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 5bed03e61bd0..84522c825ab5 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1412,7 +1412,6 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
struct mtd_info *mtd = &nor->mtd;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 mask_tb = SR_TB_BIT5;
- int shift = ffs(mask) - 1;
int pow;
if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
@@ -1424,7 +1423,7 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
*ofs = 0;
*len = 0;
} else {
- pow = ((sr & mask) ^ mask) >> shift;
+ pow = ((sr & mask) ^ mask) >> SR_BP_SHIFT;
*len = mtd->size >> pow;
if (nor->flags & SNOR_F_HAS_SR_TB && sr & mask_tb)
*ofs = 0;
@@ -1506,7 +1505,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 mask_tb = SR_TB_BIT5;
- u8 shift = ffs(mask) - 1, pow, val;
+ u8 pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
@@ -1554,7 +1553,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
*/
pow = ilog2(mtd->size) - ilog2(lock_len);
- val = mask - (pow << shift);
+ val = mask - (pow << SR_BP_SHIFT);
if (val & ~mask)
return -EINVAL;
/* Don't "lock" with no region! */
@@ -1591,7 +1590,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
int status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 mask_tb = SR_TB_BIT5;
- u8 shift = ffs(mask) - 1, pow, val;
+ u8 pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
@@ -1641,7 +1640,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if (lock_len == 0) {
val = 0; /* fully unlocked */
} else {
- val = mask - (pow << shift);
+ val = mask - (pow << SR_BP_SHIFT);
/* Some power-of-two sizes are not supported */
if (val & ~mask)
return -EINVAL;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 654992a829bd..abbe5f915410 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -136,6 +136,8 @@
#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
+#define SR_BP_SHIFT 2
+
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
--
2.17.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 4/5] mtd: spi-nor: add 4bit block protection support
[not found] ` <CGME20190821051637epcas1p363a032d32b2c20a1382bc3570aa75dd2@epcas1p3.samsung.com>
@ 2019-08-21 5:15 ` Jungseung Lee
0 siblings, 0 replies; 5+ messages in thread
From: Jungseung Lee @ 2019-08-21 5:15 UTC (permalink / raw)
To: Marek Vasut, Tudor Ambarus, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, u.kleine-koenig, linux-mtd,
js07.lee, js07.lee
Currently, we are supporting block protection only for
flash chips with 3 block protection bits in the SR register.
This patch enables block protection support for some flash with
4 block protection bits(bp0-3).
Because this feature is not universal to all flash that support
lock/unlock, control it via a new flag.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
v5:
- remake patch based on latest spi-nor/next tree
- Add BP3 handling on spi_nor_clear_sr_bp()
drivers/mtd/spi-nor/spi-nor.c | 119 +++++++++++++++++++++++++++-------
include/linux/mtd/spi-nor.h | 5 ++
2 files changed, 99 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 84522c825ab5..5cb1a6ba2c53 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -97,6 +97,7 @@ enum spi_nor_pp_command_index {
struct spi_nor_flash_parameter {
u64 size;
u32 page_size;
+ u16 n_sectors;
struct spi_nor_hwcaps hwcaps;
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
@@ -251,7 +252,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
- u16 flags;
+ u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
@@ -280,6 +281,7 @@ struct flash_info {
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
+#define SPI_NOR_HAS_BP3 BIT(16) /* use 4 bits filed for block protect */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -1410,26 +1412,49 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
uint64_t *len)
{
struct mtd_info *mtd = &nor->mtd;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 mask_tb = SR_TB_BIT5;
- int pow;
+ u8 mask_tb = SR_TB_BIT5, mask_bp3 = SR_BP3_BIT6;
+ u8 sr_masked, mask, tmp;
+ int pow = 0;
if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
- JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE) {
mask_tb = SR_TB_BIT6;
+ mask_bp3 = SR_BP3_BIT5;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = mask_bp3 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
+
+ sr_masked = sr & mask;
- if (!(sr & mask)) {
+ if (!sr_masked) {
/* No protection */
*ofs = 0;
*len = 0;
- } else {
- pow = ((sr & mask) ^ mask) >> SR_BP_SHIFT;
- *len = mtd->size >> pow;
- if (nor->flags & SNOR_F_HAS_SR_TB && sr & mask_tb)
- *ofs = 0;
+ return;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ if (sr_masked & mask_bp3 && mask_bp3 == SR_BP3_BIT6)
+ tmp = (sr_masked & ~SR_BP3_BIT6) | BIT(5);
else
- *ofs = mtd->size - *len;
+ tmp = sr_masked;
+
+ tmp >>= SR_BP_SHIFT;
+
+ if (ilog2(nor->n_sectors) >= tmp)
+ pow = ilog2(nor->n_sectors) - tmp + 1;
+ } else {
+ pow = (sr_masked ^ mask) >> SR_BP_SHIFT;
}
+
+ *len = mtd->size >> pow;
+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & mask_tb)
+ *ofs = 0;
+ else
+ *ofs = mtd->size - *len;
}
/*
@@ -1503,9 +1528,8 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 mask_tb = SR_TB_BIT5;
- u8 pow, val;
+ u8 mask_tb = SR_TB_BIT5, mask_bp3 = SR_BP3_BIT6;
+ u8 mask, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
@@ -1540,8 +1564,15 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
lock_len = ofs + len;
if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
- JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE) {
mask_tb = SR_TB_BIT6;
+ mask_bp3 = SR_BP3_BIT5;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = mask_bp3 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
/*
* Need smallest pow such that:
@@ -1553,7 +1584,17 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
*/
pow = ilog2(mtd->size) - ilog2(lock_len);
- val = mask - (pow << SR_BP_SHIFT);
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ val = ilog2(nor->n_sectors) - pow + 1;
+ val = val << SR_BP_SHIFT;
+
+ if (val & BIT(5) && mask_bp3 == SR_BP3_BIT6)
+ val = (val & ~BIT(5)) | SR_BP3_BIT6;
+ } else {
+ val = mask - (pow << SR_BP_SHIFT);
+ }
+
if (val & ~mask)
return -EINVAL;
/* Don't "lock" with no region! */
@@ -1588,9 +1629,8 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 mask_tb = SR_TB_BIT5;
- u8 pow, val;
+ u8 mask_tb = SR_TB_BIT5, mask_bp3 = SR_BP3_BIT6;
+ u8 mask, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
@@ -1625,8 +1665,16 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
lock_len = ofs;
if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
- JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE)
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE) {
mask_tb = SR_TB_BIT6;
+ mask_bp3 = SR_BP3_BIT5;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = mask_bp3 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
+
/*
* Need largest pow such that:
*
@@ -1639,13 +1687,20 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
pow = ilog2(mtd->size) - order_base_2(lock_len);
if (lock_len == 0) {
val = 0; /* fully unlocked */
+ } else if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ val = ilog2(nor->n_sectors) - pow + 1;
+ val = val << SR_BP_SHIFT;
+
+ if (val & BIT(5) && mask_bp3 == SR_BP3_BIT6)
+ val = (val & ~BIT(5)) | SR_BP3_BIT6;
} else {
val = mask - (pow << SR_BP_SHIFT);
- /* Some power-of-two sizes are not supported */
- if (val & ~mask)
- return -EINVAL;
}
+ /* Some power-of-two sizes are not supported */
+ if (val & ~mask)
+ return -EINVAL;
+
status_new = (status_old & ~mask & ~mask_tb) | val;
/* Don't protect status register if we're fully unlocked */
@@ -2026,7 +2081,17 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
static int spi_nor_clear_sr_bp(struct spi_nor *nor)
{
int ret;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 mask, mask_bp3 = SR_BP3_BIT6;
+
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND ||
+ JEDEC_MFR(nor->info) == SNOR_MFR_GIGADEVICE) {
+ mask_bp3 = SR_BP3_BIT5;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = mask_bp3 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
ret = read_sr(nor);
if (ret < 0) {
@@ -4218,6 +4283,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
memset(params, 0, sizeof(*params));
/* Set SPI NOR sizes. */
+ params->n_sectors = info->n_sectors;
params->size = (u64)info->sector_size * info->n_sectors;
params->page_size = info->page_size;
@@ -4760,12 +4826,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
if (info->flags & USE_CLSR)
nor->flags |= SNOR_F_USE_CLSR;
+ if (info->flags & SPI_NOR_HAS_BP3)
+ nor->flags |= SNOR_F_HAS_SR_BP3;
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
nor->page_size = params.page_size;
+ nor->n_sectors = params.n_sectors;
mtd->writebufsize = nor->page_size;
if (np) {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index abbe5f915410..a6b5d5e06455 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -128,7 +128,9 @@
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
+#define SR_BP3_BIT5 BIT(5) /* Block protect 3 (on Winbond/GigaDevice)*/
#define SR_TB_BIT6 BIT(6) /* Top/Bottom protect (on Winbond/GigaDevice) */
+#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
#define SR_SRWD BIT(7) /* SR write protect */
/* Spansion/Cypress specific status bits */
#define SR_E_ERR BIT(5)
@@ -247,6 +249,7 @@ enum spi_nor_option_flags {
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_4B_OPCODES = BIT(7),
SNOR_F_HAS_4BAIT = BIT(8),
+ SNOR_F_HAS_SR_BP3 = BIT(9),
};
/**
@@ -354,6 +357,7 @@ struct flash_info;
* @bouncebuf_size: size of the bounce buffer
* @info: spi-nor part JDEC MFR id and other info
* @page_size: the page size of the SPI NOR
+ * @n_sectors: number of sector
* @addr_width: number of address bytes
* @erase_opcode: the opcode for erasing a sector
* @read_opcode: the read opcode
@@ -394,6 +398,7 @@ struct spi_nor {
size_t bouncebuf_size;
const struct flash_info *info;
u32 page_size;
+ u16 n_sectors;
u8 addr_width;
u8 erase_opcode;
u8 read_opcode;
--
2.17.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v5 5/5] mtd: spi-nor: support lock/unlock for a few Micron chips
[not found] ` <CGME20190821051637epcas1p33cf6cdcfe470bc2bab971ba3695b7b98@epcas1p3.samsung.com>
@ 2019-08-21 5:15 ` Jungseung Lee
0 siblings, 0 replies; 5+ messages in thread
From: Jungseung Lee @ 2019-08-21 5:15 UTC (permalink / raw)
To: Marek Vasut, Tudor Ambarus, David Woodhouse, Brian Norris,
Boris Brezillon, Richard Weinberger, u.kleine-koenig, linux-mtd,
js07.lee, js07.lee
Some Micron models are known to have lock/unlock support,
and that also support 4bit block protection bit (bp0-3).
This patch support lock/unlock feature on the flash.
Tested on w25q512ax3. The Other is modified following the datasheet.
Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
---
v5:
- remake patch based on latest spi-nor/next tree
drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 5cb1a6ba2c53..93ca624b2a6a 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2431,8 +2431,16 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ {
+ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+ },
+ {
+ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_BP3)
+ },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
--
2.17.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-08-21 5:17 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <CGME20190821051626epcas1p4846ddc2378df756efaba78ed3a0a6057@epcas1p4.samsung.com>
2019-08-21 5:15 ` [PATCH v5 1/5] mtd: spi-nor: rename SR_TB to indicate the bit used Jungseung Lee
[not found] ` <CGME20190821051637epcas1p48d70755f6a16f04c3af59e73945b4674@epcas1p4.samsung.com>
2019-08-21 5:15 ` [PATCH v5 2/5] mtd: spi-nor: Fix wrong TB selection on winbond/gigadevice flashes Jungseung Lee
[not found] ` <CGME20190821051637epcas1p3e70e5142c92c2eebb9a9188779217b78@epcas1p3.samsung.com>
2019-08-21 5:15 ` [PATCH v5 3/5] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20190821051637epcas1p363a032d32b2c20a1382bc3570aa75dd2@epcas1p3.samsung.com>
2019-08-21 5:15 ` [PATCH v5 4/5] mtd: spi-nor: add 4bit block protection support Jungseung Lee
[not found] ` <CGME20190821051637epcas1p33cf6cdcfe470bc2bab971ba3695b7b98@epcas1p3.samsung.com>
2019-08-21 5:15 ` [PATCH v5 5/5] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
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