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From: Pratyush Yadav <me@yadavpratyush.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Pratyush Yadav <me@yadavpratyush.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	Sekhar Nori <nsekhar@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH v11 08/14] mtd: spi-nor: core: enable octal DTR mode when possible
Date: Thu, 23 Jul 2020 18:41:57 +0530	[thread overview]
Message-ID: <20200723131203.40916-9-me@yadavpratyush.com> (raw)
In-Reply-To: <20200723131203.40916-1-me@yadavpratyush.com>

From: Pratyush Yadav <p.yadav@ti.com>

Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/mtd/spi-nor/core.h |  2 ++
 2 files changed, 37 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 6efc86e2aba0..b990fc7add20 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3050,6 +3050,35 @@ static int spi_nor_init_params(struct spi_nor *nor)
 	return 0;
 }
 
+/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
+ * @nor:                 pointer to a 'struct spi_nor'
+ * @enable:              whether to enable or disable Octal DTR
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+	int ret;
+
+	if (!nor->params->octal_dtr_enable)
+		return 0;
+
+	if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
+	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
+		return 0;
+
+	ret = nor->params->octal_dtr_enable(nor, enable);
+	if (ret)
+		return ret;
+
+	if (enable)
+		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+	else
+		nor->reg_proto = SNOR_PROTO_1_1_1;
+
+	return 0;
+}
+
 /**
  * spi_nor_quad_enable() - enable/disable Quad I/O if needed.
  * @nor:                pointer to a 'struct spi_nor'
@@ -3090,6 +3119,12 @@ static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
 
+	err = spi_nor_octal_dtr_enable(nor, true);
+	if (err) {
+		dev_dbg(nor->dev, "octal mode not supported\n");
+		return err;
+	}
+
 	err = spi_nor_quad_enable(nor, true);
 	if (err) {
 		dev_dbg(nor->dev, "quad mode not supported\n");
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 27e00a9f5950..17dbbb3e4796 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -203,6 +203,7 @@ struct spi_nor_locking_ops {
  *                      higher index in the array, the higher priority.
  * @erase_map:		the erase map parsed from the SFDP Sector Map Parameter
  *                      Table.
+ * @octal_dtr_enable:	enables SPI NOR octal DTR mode.
  * @quad_enable:	enables/disables SPI NOR Quad mode.
  * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
  * @convert_addr:	converts an absolute address into something the flash
@@ -226,6 +227,7 @@ struct spi_nor_flash_parameter {
 
 	struct spi_nor_erase_map        erase_map;
 
+	int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
 	int (*quad_enable)(struct spi_nor *nor, bool enable);
 	int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
 	u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
-- 
2.27.0


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  parent reply	other threads:[~2020-07-23 13:13 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-23 13:11 [PATCH v11 00/14] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 01/14] mtd: spi-nor: core: add spi_nor_{read, write}_reg() helpers Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 02/14] mtd: spi-nor: core: add spi_nor_controller_ops_erase helper Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 03/14] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 04/14] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 05/14] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 06/14] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 07/14] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-07-23 13:11 ` Pratyush Yadav [this message]
2020-07-23 13:11 ` [PATCH v11 09/14] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-07-23 13:11 ` [PATCH v11 10/14] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-07-23 13:12 ` [PATCH v11 11/14] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-07-23 13:12 ` [PATCH v11 12/14] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-07-23 13:12 ` [PATCH v11 13/14] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-07-23 13:12 ` [PATCH v11 14/14] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav

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