* [PATCH v7 0/2] Add support for micron SPI NAND MT29F2G01AAAED
@ 2020-11-08 11:37 Thirumalesha Narasimhappa
2020-11-08 11:37 ` [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names Thirumalesha Narasimhappa
2020-11-08 11:37 ` [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED Thirumalesha Narasimhappa
0 siblings, 2 replies; 5+ messages in thread
From: Thirumalesha Narasimhappa @ 2020-11-08 11:37 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Shivamurthy Shastri, Boris Brezillon, Chuanhong Guo, linux-mtd,
linux-kernel
Cc: Thirumalesha Narasimhappa
Adding support for Micron SPI NAND MT29F2G01AAAED device and generalised
the structure names as per the review comments
v7: Reverted to the v4 except ECC structure related changes
v6: Reverted the SPINAND_OP_VARIANTS() as they were in v4 for
MT29F2G01AAAED device
v5: As per the review comments, the changes were reverted to the v2,
except the MT29F2G01AAAED device related (including the review comments)
v4: Split patch into two parts,
1. Generalise the oob structure name & function names as show in v3
2. Add support for MT29F2G01AAAED device
a. Add oob section check in micron_ooblayout_free function
b. Rename mt29f2g01aaaed_* to generic name micron_4_*
v3: As per the review comments,
1. Renamed read_cache_variants as quadio_read_cache_variants,
write_cache_variants as
x4_write_cache_variants/x1_write_cache_variants,
update_cache_variants as
x4_update_cache_variants/x1_update_cache_variants,
read_cache_variants as x4_read_cache_variants
2. Renamed micron_8_ooblayout as micron_grouped_ooblayout &
mt29f2g01aaaed_ooblayout as
micron_interleaved_ooblayout
3. Generalized page size based oob section check in
mt29f2g01aaaed_ooblayout_ecc function
and separate case check for two bytes BBM reserved in
mt29f2g01aaaed_ooblayout_free function
4. Removed mt29f2g01aaaed_ecc_get_status function &
MICRON_STATUS_ECC_1TO4_BITFLIPS
v2: Removed SPINAND_SELECT_TARGET as per the comments & fixed typo
errors
v1: Add support for Micron SPI Nand device MT29F2G01AAAED
Thirumalesha Narasimhappa (2):
mtd: spinand: micron: Generalize the structure names
mtd: spinand: micron: Add support for MT29F2G01AAAED
drivers/mtd/nand/spi/micron.c | 124 ++++++++++++++++++++++++++--------
1 file changed, 94 insertions(+), 30 deletions(-)
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names
2020-11-08 11:37 [PATCH v7 0/2] Add support for micron SPI NAND MT29F2G01AAAED Thirumalesha Narasimhappa
@ 2020-11-08 11:37 ` Thirumalesha Narasimhappa
2020-12-07 11:10 ` Miquel Raynal
2020-11-08 11:37 ` [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED Thirumalesha Narasimhappa
1 sibling, 1 reply; 5+ messages in thread
From: Thirumalesha Narasimhappa @ 2020-11-08 11:37 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Shivamurthy Shastri, Boris Brezillon, Chuanhong Guo, linux-mtd,
linux-kernel
Cc: Thirumalesha Narasimhappa
Rename the read/write/update of SPINAND_OP_VARIANTS() to a generic names
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
---
drivers/mtd/nand/spi/micron.c | 60 +++++++++++++++++------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 5d370cfcdaaa..afe3ba37dcfb 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -28,7 +28,7 @@
#define MICRON_SELECT_DIE(x) ((x) << 6)
-static SPINAND_OP_VARIANTS(read_cache_variants,
+static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -36,11 +36,11 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-static SPINAND_OP_VARIANTS(write_cache_variants,
+static SPINAND_OP_VARIANTS(x4_write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
-static SPINAND_OP_VARIANTS(update_cache_variants,
+static SPINAND_OP_VARIANTS(x4_update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
@@ -120,9 +120,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -131,9 +131,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -142,9 +142,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -153,9 +153,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -164,9 +164,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
0,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
@@ -176,9 +176,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -187,9 +187,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status)),
@@ -198,9 +198,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
@@ -210,9 +210,9 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
+ &x4_write_cache_variants,
+ &x4_update_cache_variants),
SPINAND_HAS_CR_FEAT_BIT,
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED
2020-11-08 11:37 [PATCH v7 0/2] Add support for micron SPI NAND MT29F2G01AAAED Thirumalesha Narasimhappa
2020-11-08 11:37 ` [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names Thirumalesha Narasimhappa
@ 2020-11-08 11:37 ` Thirumalesha Narasimhappa
2020-12-07 11:09 ` Miquel Raynal
1 sibling, 1 reply; 5+ messages in thread
From: Thirumalesha Narasimhappa @ 2020-11-08 11:37 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Shivamurthy Shastri, Boris Brezillon, Chuanhong Guo, linux-mtd,
linux-kernel
Cc: Thirumalesha Narasimhappa
The MT29F2G01AAAED is a single die, 2Gb Micron SPI NAND Flash with 4-bit
ECC
Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
---
drivers/mtd/nand/spi/micron.c | 64 +++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index afe3ba37dcfb..50b7295bc922 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -44,6 +44,19 @@ static SPINAND_OP_VARIANTS(x4_update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+/* Micron MT29F2G01AAAED Device */
+static SPINAND_OP_VARIANTS(x4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(x1_write_cache_variants,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(x1_update_cache_variants,
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -74,6 +87,47 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
.free = micron_8_ooblayout_free,
};
+static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct spinand_device *spinand = mtd_to_spinand(mtd);
+
+ if (section >= spinand->base.memorg.pagesize /
+ mtd->ecc_step_size)
+ return -ERANGE;
+
+ region->offset = (section * 16) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int micron_4_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ struct spinand_device *spinand = mtd_to_spinand(mtd);
+
+ if (section >= spinand->base.memorg.pagesize /
+ mtd->ecc_step_size)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 16 * section;
+ region->length = 8;
+ } else {
+ /* section 0 has two bytes reserved for the BBM */
+ region->offset = 2;
+ region->length = 6;
+ }
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops micron_4_ooblayout = {
+ .ecc = micron_4_ooblayout_ecc,
+ .free = micron_4_ooblayout_free,
+};
+
static int micron_select_target(struct spinand_device *spinand,
unsigned int target)
{
@@ -217,6 +271,16 @@ static const struct spinand_info micron_spinand_table[] = {
SPINAND_ECCINFO(µn_8_ooblayout,
micron_8_ecc_get_status),
SPINAND_SELECT_TARGET(micron_select_target)),
+ /* M69A 2Gb 3.3V */
+ SPINAND_INFO("MT29F2G01AAAED",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
+ &x1_write_cache_variants,
+ &x1_update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(µn_4_ooblayout, NULL)),
};
static int micron_spinand_init(struct spinand_device *spinand)
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED
2020-11-08 11:37 ` [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED Thirumalesha Narasimhappa
@ 2020-12-07 11:09 ` Miquel Raynal
0 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2020-12-07 11:09 UTC (permalink / raw)
To: Thirumalesha Narasimhappa, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Shivamurthy Shastri, Boris Brezillon,
Chuanhong Guo, linux-mtd, linux-kernel
On Sun, 2020-11-08 at 11:37:35 UTC, Thirumalesha Narasimhappa wrote:
> The MT29F2G01AAAED is a single die, 2Gb Micron SPI NAND Flash with 4-bit
> ECC
>
> Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@gmail.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names
2020-11-08 11:37 ` [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names Thirumalesha Narasimhappa
@ 2020-12-07 11:10 ` Miquel Raynal
0 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2020-12-07 11:10 UTC (permalink / raw)
To: Thirumalesha Narasimhappa
Cc: Vignesh Raghavendra, Richard Weinberger, linux-kernel,
Boris Brezillon, linux-mtd, Chuanhong Guo, Shivamurthy Shastri
Hi Thirumalesha,
Thirumalesha Narasimhappa <nthirumalesha7@gmail.com> wrote on Sun, 8
Nov 2020 19:37:34 +0800:
> Rename the read/write/update of SPINAND_OP_VARIANTS() to a generic names
I applied this patch with a minor change: it's not a generalization of
the name, but quite the opposite.
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-12-07 11:11 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-08 11:37 [PATCH v7 0/2] Add support for micron SPI NAND MT29F2G01AAAED Thirumalesha Narasimhappa
2020-11-08 11:37 ` [PATCH v7 1/2] mtd: spinand: micron: Generalize the structure names Thirumalesha Narasimhappa
2020-12-07 11:10 ` Miquel Raynal
2020-11-08 11:37 ` [PATCH v7 2/2] mtd: spinand: micron: Add support for MT29F2G01AAAED Thirumalesha Narasimhappa
2020-12-07 11:09 ` Miquel Raynal
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).