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From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>
Cc: vigneshr@ti.com, richard@nod.at, linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com
Subject: Re: [PATCH] mtd: spi-nor: Fix quad enable for Spansion like flashes
Date: Thu, 16 Jan 2020 10:35:12 +0000
Message-ID: <2180698.lX2pLR0Ns3@localhost.localdomain> (raw)
In-Reply-To: <20200116093700.28308-1-michael@walle.cc>

On Thursday, January 16, 2020 11:37:00 AM EET Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> The commit 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable
> methods") forgot to actually set the QE bit in some cases. Thus this
> breaks quad mode accesses to flashes which support readback of the
> status register-2. Fix it.
> 
> Fixes: 7b678c69c0ca ("mtd: spi-nor: Merge spansion Quad Enable methods")
> Signed-off-by: Michael Walle <michael@walle.cc>

Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Thanks, Michael!
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index addb6319fcbb..ea0429448207 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2140,6 +2140,8 @@ static int spi_nor_sr2_bit1_quad_enable(struct spi_nor
> *nor) if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
>                 return 0;
> 
> +       nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
> +
>         return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
>  }
> 
> --
> 2.20.1




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Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-16  9:37 Michael Walle
2020-01-16 10:35 ` Tudor.Ambarus [this message]
2020-01-17 13:58 ` Tudor.Ambarus
2020-01-17 21:47 ` Miquel Raynal

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