From: <Tudor.Ambarus@microchip.com>
To: <p.yadav@ti.com>
Cc: alexandre.belloni@bootlin.com, masonccyang@mxic.com.tw,
vigneshr@ti.com, richard@nod.at, nsekhar@ti.com,
Nicolas.Ferre@microchip.com, boris.brezillon@collabora.com,
michal.simek@xilinx.com, Ludovic.Desroches@microchip.com,
broonie@kernel.org, linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, miquel.raynal@bootlin.com,
matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal
Date: Sat, 30 May 2020 18:42:25 +0000 [thread overview]
Message-ID: <2267830.vuSd8QnXzO@192.168.0.120> (raw)
In-Reply-To: <20200525091544.17270-14-p.yadav@ti.com>
On Monday, May 25, 2020 12:15:38 PM EEST Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The Micron MT35XU512ABA flash does not support the quad enable bit. But
> instead of programming the Quad Enable Require field to 000b ("Device
> does not have a QE bit"), it is programmed to 111b ("Reserved").
>
> While this is technically incorrect, it is not reason enough to abort
> BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
> enable bit present.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
> drivers/mtd/spi-nor/sfdp.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 052cabb52df9..9fd3d8d9a127 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
>
> /* Quad Enable Requirements. */
> switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
> - case BFPT_DWORD15_QER_NONE:
> - params->quad_enable = NULL;
> - break;
> -
> case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
> /*
> * Writing only one byte to the Status Register has the
> @@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> break;
>
> + case BFPT_DWORD15_QER_NONE:
> default:
> - return -EINVAL;
> + params->quad_enable = NULL;
> + break;
I would just add a dev_dbg message and break the switch.
dev_dbg(nor->dev, "BFPT QER reserved value used.\n");
break;
You will then have to set params->quad_enable = NULL; in a post_bfpt hook.
Cheers,
ta
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next prev parent reply other threads:[~2020-05-30 18:43 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-25 9:15 [PATCH v9 00/19] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 01/19] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 02/19] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 03/19] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 04/19] spi: spi-mtk-nor: " Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 05/19] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths Pratyush Yadav
2020-05-30 18:49 ` Tudor.Ambarus
2020-05-25 9:15 ` [PATCH v9 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-05-30 18:50 ` Tudor.Ambarus
2020-05-25 9:15 ` [PATCH v9 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 12/19] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-05-30 18:42 ` Tudor.Ambarus [this message]
2020-06-01 8:58 ` Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-05-25 9:15 ` [PATCH v9 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
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