Re: [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue

["Wojtaszczyk, Piotr" <WojtaszczykP@cumminsallison.com>]

On 1/14/20 3:12 AM, Miquel Raynal wrote:
> Crap. I'll not resend immediately as this is an RFC, I expect
> feedback on this proposal before sending an actual patch.
> 
> 
> Thanks,
> Miquèl
> 

Hi Miquèl, here are some my comments:

+static int micron_nand_avoid_shallow_erase(struct nand_chip *chip,
+					   unsigned int eb)
+{
+	struct micron_nand *micron = nand_get_manufacturer_data(chip);
+	unsigned int page = eb * nanddev_pages_per_eraseblock(&chip->base);
+	u8 *databuf = nand_get_data_buf(chip);
+	int ret, i;
+
+	memset(databuf, 0xFF, nanddev_page_size(&chip->base));
+
+	/* Micron advises to only write odd pages */
+	for (i = 0; i < MICRON_SHALLOW_ERASE_MIN_PAGE; i += 2, page += 2) {
+		if (!(micron->writtenp[eb] & BIT(i))) {
+			ret = nand_write_page_raw(chip, databuf, false, page);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}

Shouldn't we program only the OOB area of the pages to 0'es? Programming pages to 0xFF 
which are already 0xFF takes more time and doesn't make any difference.

Also after power loss all flags in micron->writtenp are gone so the 
micron_nand_avoid_shallow_erase will perform on all PEBs causing performance loss.

Instead we could check a flag in OOB area of first page of the PEB we are about to erase 
and clear the flag bit/bits when 16th page of the PEB gets programmed. Simmilar to bad 
block mark.

--
Peter W.
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