Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver

From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: John Garry <john.garry@huawei.com>
Cc: Jiancheng Xue <xuejiancheng@hisilicon.com>,
	chenxiang66@hisilicon.com,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	tudor.ambarus@microchip.com, Linuxarm <linuxarm@huawei.com>,
	linux-spi <linux-spi@vger.kernel.org>,
	Marek Vasut <marek.vasut@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	"open list:MEMORY TECHNOLOGY..." <linux-mtd@lists.infradead.org>,
	liusimin4@huawei.com,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	wanghuiqiang <wanghuiqiang@huawei.com>,
	fengsheng5@huawei.com
Subject: Re: [PATCH v2 2/3] spi: Add HiSilicon v3xx SPI NOR flash controller driver
Date: Fri, 31 Jan 2020 13:39:19 +0200	[thread overview]
Message-ID: <CAHp75Ve=ZwJe2XV8Y1UN6sMe1ZHOBwUtRUD=aGqhR4Gc7BNUcg@mail.gmail.com> (raw)
In-Reply-To: <0252a76d-7e2b-2c70-8b1b-0d041d972098@huawei.com>

On Fri, Jan 31, 2020 at 12:08 PM John Garry <john.garry@huawei.com> wrote:
>
> On 13/01/2020 14:34, Andy Shevchenko wrote:
> > On Mon, Jan 13, 2020 at 02:27:54PM +0000, Mark Brown wrote:
> >> On Mon, Jan 13, 2020 at 04:17:32PM +0200, Andy Shevchenko wrote:
> >>> On Mon, Jan 13, 2020 at 4:07 PM Mark Brown <broonie@kernel.org> wrote:
> >>>> On Mon, Jan 13, 2020 at 01:01:06PM +0000, John Garry wrote:
> >>>>> On 13/01/2020 11:42, Mark Brown wrote:
> >>
> >>>>>> The idiomatic approach appears to be for individual board vendors
> >>>>>> to allocate IDs, you do end up with multiple IDs from multiple
> >>>>>> vendors for the same thing.
> >>
> >>>>> But I am not sure how appropriate that same approach would be for some 3rd
> >>>>> party memory part which we're simply wiring up on our board. Maybe it is.
> >>
> >>>> It seems to be quite common for Intel reference designs to assign
> >>>> Intel IDs to non-Intel parts on the board (which is where I
> >>>> became aware of this practice).
> >>
> >>> Basically vendor of component in question is responsible for ID, but
> >>> it seems they simple don't care.
> >>
> >> AFAICT a lot of the time it seems to be that whoever is writing
> >> the software ends up assigning an ID, that may not be the silicon
> >> vendor.
> >
> > ...which is effectively abusing the ACPI ID allocation procedure.
> >
> > (And yes, Intel itself did it in the past — see badly created ACPI IDs
> >   in the drivers)
> >
>
> Hi Mark,
>
> About this topic of ACPI having no method to describe device buswidth in
> the resource descriptor, it may be an idea for me to raise a Tianocore
> feature request @ https://bugzilla.tianocore.org/
>

The 19.6.126 describes the SPI resource, in particular:

---8<---8<---
DataBitLength is the size, in bits, of the smallest transfer unit for
this connection. _LEN is automatically
created to refer to this portion of the resource descriptor.
---8<---8<---

Is it what you are looking for? (As far as I know most of the
firmwares simple abuse this field among others)

> There seems to be an avenue there for raising new features for the spec.
> I (or my org) can't participate in AWSG.

But have you read 19.6.126?

> I would have no concrete proposal for spec update for now, though.
> Hopefully others with more expertise could contribute.

-- 
With Best Regards,
Andy Shevchenko

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