Re: [PATCH] mtd: spi-nor: Add Micron MT25QU128 support

Re: [PATCH] mtd: spi-nor: Add Micron MT25QU128 support

[Vignesh Raghavendra]

On 02/04/19 8:29 PM, wan.ahmad.zainie.wan.mohamad@intel.com wrote:
> From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> 
> Add support for Micron 128Mb Serial NOR Flash Memory.
> Datasheet is available: MT25Q_QLHS_U_128_ABA_0.pdf
> 

Could you add what board was this tested on and what modes were tested?

> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index fae147452aff..626ac9e02241 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1881,6 +1881,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
>  	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>  	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>  	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> +	{ "mt25qu128",   INFO(0x20bb18, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>  

Per datasheet here[1] mt25qu128 does seem to support CHIP erase. So please drop NO_CHIP_ERASE.
Micron flash ID table is sorted by device ID. Could you insert the entry accordingly?
Also, please limit the line to 80 char like:

        { "mt25qu128",   INFO(0x20bb18, 0, 64 * 1024, 1024, SECT_4K | 
                         USE_FSR | SPI_NOR_QUAD_READ) },


[1] https://www.mouser.com/datasheet/2/671/MT25Q_QLHS_U_128_ABA_0-1387216.pdf

>  	/* Micron */
>  	{
> 

-- 
Regards
Vignesh

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[PATCH] mtd: spi-nor: Add Micron MT25QU128 support

[wan.ahmad.zainie.wan.mohamad]

From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

Add support for Micron 128Mb Serial NOR Flash Memory.
Datasheet is available: MT25Q_QLHS_U_128_ABA_0.pdf

Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index fae147452aff..626ac9e02241 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1881,6 +1881,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+	{ "mt25qu128",   INFO(0x20bb18, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 
 	/* Micron */
 	{
-- 
1.9.1


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RE: [PATCH] mtd: spi-nor: Add Micron MT25QU128 support

[Wan Mohamad, Wan Ahmad Zainie]

> -----Original Message-----
> From: Vignesh Raghavendra [mailto:vigneshr@ti.com]
> Sent: Tuesday, April 2, 2019 4:06 PM
> To: Wan Mohamad, Wan Ahmad Zainie
> <wan.ahmad.zainie.wan.mohamad@intel.com>; linux-
> mtd@lists.infradead.org; marek.vasut@gmail.com;
> tudor.ambarus@microchip.com; dwmw2@infradead.org;
> computersforpeace@gmail.com; bbrezillon@kernel.org; richard@nod.at
> Subject: Re: [PATCH] mtd: spi-nor: Add Micron MT25QU128 support
> 
> 
> 
> On 02/04/19 8:29 PM, wan.ahmad.zainie.wan.mohamad@intel.com wrote:
> > From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> >
> > Add support for Micron 128Mb Serial NOR Flash Memory.
> > Datasheet is available: MT25Q_QLHS_U_128_ABA_0.pdf
> >
> 
> Could you add what board was this tested on and what modes were tested?
> 

Noted. I will add this information in the next submission.
The test is done with FPGA environment.

> > Signed-off-by: Wan Ahmad Zainie
> > <wan.ahmad.zainie.wan.mohamad@intel.com>
> > ---
> >  drivers/mtd/spi-nor/spi-nor.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index fae147452aff..626ac9e02241
> > 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1881,6 +1881,7 @@ static int sr2_bit7_quad_enable(struct spi_nor
> *nor)
> >  	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >  	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >  	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > +	{ "mt25qu128",   INFO(0x20bb18, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> 
> Per datasheet here[1] mt25qu128 does seem to support CHIP erase. So
> please drop NO_CHIP_ERASE.
> Micron flash ID table is sorted by device ID. Could you insert the entry
> accordingly?
> Also, please limit the line to 80 char like:
> 
>         { "mt25qu128",   INFO(0x20bb18, 0, 64 * 1024, 1024, SECT_4K |
>                          USE_FSR | SPI_NOR_QUAD_READ) },
> 

Noted. I will change accordingly.

> 
> [1]
> https://www.mouser.com/datasheet/2/671/MT25Q_QLHS_U_128_ABA_0-
> 1387216.pdf
> 
> >  	/* Micron */
> >  	{
> >
> 
> --
> Regards
> Vignesh

Thank you.

Best regards,
Zainie
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