From: Michael Walle <michael@walle.cc>
To: Eliav Farber <farbere@amazon.com>
Cc: tudor.ambarus@microchip.com, pratyush@kernel.org,
miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
talel@amazon.com, jonnyc@amazon.com, hhhawa@amazon.com,
hanochu@amazon.com, itamark@amazon.com, shellykz@amazon.com,
amitlavi@amazon.com, dkl@amazon.com
Subject: Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
Date: Thu, 20 Oct 2022 12:46:33 +0200 [thread overview]
Message-ID: <d91e3d91f085390d5dbe0c4415c9e37f@walle.cc> (raw)
In-Reply-To: <20221020092058.33844-1-farbere@amazon.com>
Am 2022-10-20 11:20, schrieb Eliav Farber:
> mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on MT25QU256ABA8ESF-0SIT.
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
>
> Signed-off-by: Eliav Farber <farbere@amazon.com>
> Link:
> https://lore.kernel.org/lkml/20221019071631.15191-1-farbere@amazon.com
Reviewed-by: Michael Walle <michael@walle.cc>
Thanks,
-michael
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next prev parent reply other threads:[~2022-10-20 11:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:20 [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a Eliav Farber
2022-10-20 10:46 ` Michael Walle [this message]
2022-11-21 15:11 ` Tudor Ambarus
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