* linux-next: build failure after merge of the tip tree
@ 2020-06-21 6:33 Stephen Rothwell
2020-06-21 10:53 ` Borislav Petkov
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Rothwell @ 2020-06-21 6:33 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra
Cc: Linux Next Mailing List, Linux Kernel Mailing List,
Borislav Petkov, Guenter Roeck
[-- Attachment #1: Type: text/plain, Size: 708 bytes --]
Hi all,
After merging the tip tree, today's linux-next build (perf) failed
like this:
In file included from trace/beauty/tracepoints/x86_msr.c:10:
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
| ^~~~~~~~~~~
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
Caused by commit
1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
I have used the tip tree from next-20200618 for tooday.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: linux-next: build failure after merge of the tip tree
2020-06-21 6:33 linux-next: build failure after merge of the tip tree Stephen Rothwell
@ 2020-06-21 10:53 ` Borislav Petkov
2020-06-22 1:38 ` Stephen Rothwell
0 siblings, 1 reply; 6+ messages in thread
From: Borislav Petkov @ 2020-06-21 10:53 UTC (permalink / raw)
To: Stephen Rothwell, Arnaldo Carvalho de Melo
Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra,
Linux Next Mailing List, Linux Kernel Mailing List,
Guenter Roeck
+ acme for an FYI.
On Sun, Jun 21, 2020 at 04:33:23PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the tip tree, today's linux-next build (perf) failed
> like this:
>
> In file included from trace/beauty/tracepoints/x86_msr.c:10:
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
> 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
> | ^~~~~~~~~~~
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
>
> Caused by commit
>
> 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
>
> I have used the tip tree from next-20200618 for tooday.
Thanks, I saw that once but then got distracted to something of higher
prio. :-\
I'll apply this after testing it a bit:
---
From: Borislav Petkov <bp@suse.de>
Date: Sun, 21 Jun 2020 12:41:53 +0200
Subject: [PATCH] x86/msr: Move the F15h MSRs where they belong
1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
moved the three F15h power MSRs to the architectural list but that was
wrong as they belong in the family 0x15 list. That also caused:
In file included from trace/beauty/tracepoints/x86_msr.c:10:
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
| ^~~~~~~~~~~
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
due to MSR_F15H_PTSC ending up being defined twice. Move them where they
belong and drop the duplicate.
While at it, update the msr-index.h copy to pick up the changes from
7e5b3c267d25 ("x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation")
Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/include/asm/msr-index.h | 5 ++---
tools/arch/x86/include/asm/msr-index.h | 9 ++++++---
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index eb9537254920..63ed8fe35738 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -422,11 +422,8 @@
#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
-#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
-#define MSR_F15H_PTSC 0xc0010280
#define MSR_AMD_PPIN_CTL 0xc00102f0
#define MSR_AMD_PPIN 0xc00102f1
#define MSR_AMD64_CPUID_FN_1 0xc0011004
@@ -469,6 +466,8 @@
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
/* Fam 15h MSRs */
+#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 7dfd45bb6cdb..63ed8fe35738 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -128,6 +128,10 @@
#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
+/* SRBDS support */
+#define MSR_IA32_MCU_OPT_CTRL 0x00000123
+#define RNGDS_MITG_DIS BIT(0)
+
#define MSR_IA32_SYSENTER_CS 0x00000174
#define MSR_IA32_SYSENTER_ESP 0x00000175
#define MSR_IA32_SYSENTER_EIP 0x00000176
@@ -418,11 +422,8 @@
#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
-#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
-#define MSR_F15H_PTSC 0xc0010280
#define MSR_AMD_PPIN_CTL 0xc00102f0
#define MSR_AMD_PPIN 0xc00102f1
#define MSR_AMD64_CPUID_FN_1 0xc0011004
@@ -465,6 +466,8 @@
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
/* Fam 15h MSRs */
+#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
--
2.21.0
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: linux-next: build failure after merge of the tip tree
2020-06-21 10:53 ` Borislav Petkov
@ 2020-06-22 1:38 ` Stephen Rothwell
2020-06-22 13:04 ` [PATCH -v2] x86/msr: Move the F15h MSRs where they belong Borislav Petkov
0 siblings, 1 reply; 6+ messages in thread
From: Stephen Rothwell @ 2020-06-22 1:38 UTC (permalink / raw)
To: Borislav Petkov
Cc: Arnaldo Carvalho de Melo, Thomas Gleixner, Ingo Molnar,
H. Peter Anvin, Peter Zijlstra, Linux Next Mailing List,
Linux Kernel Mailing List, Guenter Roeck
[-- Attachment #1: Type: text/plain, Size: 5324 bytes --]
Hi Borislav,
On Sun, 21 Jun 2020 12:53:50 +0200 Borislav Petkov <bp@alien8.de> wrote:
>
> + acme for an FYI.
>
> On Sun, Jun 21, 2020 at 04:33:23PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the tip tree, today's linux-next build (perf) failed
> > like this:
> >
> > In file included from trace/beauty/tracepoints/x86_msr.c:10:
> > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
> > 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
> > | ^~~~~~~~~~~
> > perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
> >
> > Caused by commit
> >
> > 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
> >
> > I have used the tip tree from next-20200618 for tooday.
>
> Thanks, I saw that once but then got distracted to something of higher
> prio. :-\
>
> I'll apply this after testing it a bit:
>
> ---
> From: Borislav Petkov <bp@suse.de>
> Date: Sun, 21 Jun 2020 12:41:53 +0200
> Subject: [PATCH] x86/msr: Move the F15h MSRs where they belong
>
> 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
>
> moved the three F15h power MSRs to the architectural list but that was
> wrong as they belong in the family 0x15 list. That also caused:
>
> In file included from trace/beauty/tracepoints/x86_msr.c:10:
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
> 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
> | ^~~~~~~~~~~
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
>
> due to MSR_F15H_PTSC ending up being defined twice. Move them where they
> belong and drop the duplicate.
>
> While at it, update the msr-index.h copy to pick up the changes from
>
> 7e5b3c267d25 ("x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation")
>
> Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> ---
> arch/x86/include/asm/msr-index.h | 5 ++---
> tools/arch/x86/include/asm/msr-index.h | 9 ++++++---
> 2 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index eb9537254920..63ed8fe35738 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -422,11 +422,8 @@
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> #define MSR_AMD64_CPUID_FN_1 0xc0011004
> @@ -469,6 +466,8 @@
> #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
>
> /* Fam 15h MSRs */
> +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_F15H_PERF_CTL 0xc0010200
> #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index 7dfd45bb6cdb..63ed8fe35738 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -128,6 +128,10 @@
> #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
> #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
>
> +/* SRBDS support */
> +#define MSR_IA32_MCU_OPT_CTRL 0x00000123
> +#define RNGDS_MITG_DIS BIT(0)
> +
> #define MSR_IA32_SYSENTER_CS 0x00000174
> #define MSR_IA32_SYSENTER_ESP 0x00000175
> #define MSR_IA32_SYSENTER_EIP 0x00000176
> @@ -418,11 +422,8 @@
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> #define MSR_AMD64_CPUID_FN_1 0xc0011004
> @@ -465,6 +466,8 @@
> #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
>
> /* Fam 15h MSRs */
> +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_F15H_PERF_CTL 0xc0010200
> #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
I applied that patch to the tip tree merge today.
Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # build tested
--
Cheers,
Stephen Rothwell
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH -v2] x86/msr: Move the F15h MSRs where they belong
2020-06-22 1:38 ` Stephen Rothwell
@ 2020-06-22 13:04 ` Borislav Petkov
2020-06-22 14:17 ` Arnaldo Carvalho de Melo
0 siblings, 1 reply; 6+ messages in thread
From: Borislav Petkov @ 2020-06-22 13:04 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Arnaldo Carvalho de Melo, Thomas Gleixner, Ingo Molnar,
H. Peter Anvin, Peter Zijlstra, Linux Next Mailing List,
Linux Kernel Mailing List, Guenter Roeck
On Mon, Jun 22, 2020 at 11:38:24AM +1000, Stephen Rothwell wrote:
> I applied that patch to the tip tree merge today.
>
> Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # build tested
Here's v2 instead, addressing acme's request. I didn't rebase the
x86/cleanups branch because I'd like to have this case documented.
acme, ACK?
Thx.
---
From c1c1a26bc631fafb68ed30c5164d0231acc500ee Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@suse.de>
Date: Sun, 21 Jun 2020 12:41:53 +0200
1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
moved the three F15h power MSRs to the architectural list but that was
wrong as they belong in the family 0x15 list. That also caused:
In file included from trace/beauty/tracepoints/x86_msr.c:10:
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
| ^~~~~~~~~~~
perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
due to MSR_F15H_PTSC ending up being defined twice. Move them where they
belong and drop the duplicate.
Also, drop the respective tools/ changes of the msr-index.h copy the
above commit added because perf tool developers prefer to go through
those changes themselves in order to figure out whether changes to the
kernel headers would need additional handling in perf.
Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200621163323.14e8533f@canb.auug.org.au
---
arch/x86/include/asm/msr-index.h | 5 ++---
tools/arch/x86/include/asm/msr-index.h | 5 +----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index eb9537254920..63ed8fe35738 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -422,11 +422,8 @@
#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
-#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
-#define MSR_F15H_PTSC 0xc0010280
#define MSR_AMD_PPIN_CTL 0xc00102f0
#define MSR_AMD_PPIN 0xc00102f1
#define MSR_AMD64_CPUID_FN_1 0xc0011004
@@ -469,6 +466,8 @@
#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
/* Fam 15h MSRs */
+#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 7dfd45bb6cdb..ef452b817f44 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -414,18 +414,15 @@
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
+#define MSR_AMD64_CPUID_FN_1 0xc0011004
#define MSR_AMD64_PATCH_LOADER 0xc0010020
#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_AMD_PERF_STATUS 0xc0010063
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
-#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
-#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
-#define MSR_F15H_PTSC 0xc0010280
#define MSR_AMD_PPIN_CTL 0xc00102f0
#define MSR_AMD_PPIN 0xc00102f1
-#define MSR_AMD64_CPUID_FN_1 0xc0011004
#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
#define MSR_AMD64_BU_CFG2 0xc001102a
--
2.21.0
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH -v2] x86/msr: Move the F15h MSRs where they belong
2020-06-22 13:04 ` [PATCH -v2] x86/msr: Move the F15h MSRs where they belong Borislav Petkov
@ 2020-06-22 14:17 ` Arnaldo Carvalho de Melo
2020-06-22 15:15 ` Borislav Petkov
0 siblings, 1 reply; 6+ messages in thread
From: Arnaldo Carvalho de Melo @ 2020-06-22 14:17 UTC (permalink / raw)
To: Borislav Petkov
Cc: Stephen Rothwell, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
Peter Zijlstra, Linux Next Mailing List,
Linux Kernel Mailing List, Guenter Roeck
Em Mon, Jun 22, 2020 at 03:04:07PM +0200, Borislav Petkov escreveu:
> On Mon, Jun 22, 2020 at 11:38:24AM +1000, Stephen Rothwell wrote:
> > I applied that patch to the tip tree merge today.
> >
> > Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # build tested
>
> Here's v2 instead, addressing acme's request. I didn't rebase the
> x86/cleanups branch because I'd like to have this case documented.
>
> acme, ACK?
So this reverts the change you made to the tools copy of that file and
then does the change you need to the kernel sources, ok.
In the future the change will be made just in the kernel files, as
kernel developers don't have to have the burden of checking if tooling
continues to work when they change kernel files.
That way later the perf developers get the warning in the perf build
process, see how this change in a file that is a copy from the kernel
sources affects tooling, and act upon it, simply updating the copy or
doing that + extra tooling adjustments, perhaps a new feature, etc.
Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>
- Arnaldo
> Thx.
>
> ---
> From c1c1a26bc631fafb68ed30c5164d0231acc500ee Mon Sep 17 00:00:00 2001
> From: Borislav Petkov <bp@suse.de>
> Date: Sun, 21 Jun 2020 12:41:53 +0200
>
> 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
>
> moved the three F15h power MSRs to the architectural list but that was
> wrong as they belong in the family 0x15 list. That also caused:
>
> In file included from trace/beauty/tracepoints/x86_msr.c:10:
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: error: initialized field overwritten [-Werror=override-init]
> 292 | [0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
> | ^~~~~~~~~~~
> perf/trace/beauty/generated/x86_arch_MSRs_array.c:292:45: note: (near initialization for 'x86_AMD_V_KVM_MSRs[640]')
>
> due to MSR_F15H_PTSC ending up being defined twice. Move them where they
> belong and drop the duplicate.
>
> Also, drop the respective tools/ changes of the msr-index.h copy the
> above commit added because perf tool developers prefer to go through
> those changes themselves in order to figure out whether changes to the
> kernel headers would need additional handling in perf.
>
> Fixes: 1068ed4547ad ("x86/msr: Lift AMD family 0x15 power-specific MSRs")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Signed-off-by: Borislav Petkov <bp@suse.de>
> Link: https://lkml.kernel.org/r/20200621163323.14e8533f@canb.auug.org.au
> ---
> arch/x86/include/asm/msr-index.h | 5 ++---
> tools/arch/x86/include/asm/msr-index.h | 5 +----
> 2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index eb9537254920..63ed8fe35738 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -422,11 +422,8 @@
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> #define MSR_AMD64_CPUID_FN_1 0xc0011004
> @@ -469,6 +466,8 @@
> #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
>
> /* Fam 15h MSRs */
> +#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> +#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_F15H_PERF_CTL 0xc0010200
> #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index 7dfd45bb6cdb..ef452b817f44 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -414,18 +414,15 @@
> #define MSR_AMD64_PATCH_LEVEL 0x0000008b
> #define MSR_AMD64_TSC_RATIO 0xc0000104
> #define MSR_AMD64_NB_CFG 0xc001001f
> +#define MSR_AMD64_CPUID_FN_1 0xc0011004
> #define MSR_AMD64_PATCH_LOADER 0xc0010020
> #define MSR_AMD_PERF_CTL 0xc0010062
> #define MSR_AMD_PERF_STATUS 0xc0010063
> #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
> -#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
> -#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
> #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
> #define MSR_AMD64_OSVW_STATUS 0xc0010141
> -#define MSR_F15H_PTSC 0xc0010280
> #define MSR_AMD_PPIN_CTL 0xc00102f0
> #define MSR_AMD_PPIN 0xc00102f1
> -#define MSR_AMD64_CPUID_FN_1 0xc0011004
> #define MSR_AMD64_LS_CFG 0xc0011020
> #define MSR_AMD64_DC_CFG 0xc0011022
> #define MSR_AMD64_BU_CFG2 0xc001102a
> --
> 2.21.0
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
--
- Arnaldo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH -v2] x86/msr: Move the F15h MSRs where they belong
2020-06-22 14:17 ` Arnaldo Carvalho de Melo
@ 2020-06-22 15:15 ` Borislav Petkov
0 siblings, 0 replies; 6+ messages in thread
From: Borislav Petkov @ 2020-06-22 15:15 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: Stephen Rothwell, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
Peter Zijlstra, Linux Next Mailing List,
Linux Kernel Mailing List, Guenter Roeck
On Mon, Jun 22, 2020 at 11:17:37AM -0300, Arnaldo Carvalho de Melo wrote:
> So this reverts the change you made to the tools copy of that file and
> then does the change you need to the kernel sources, ok.
>
> In the future the change will be made just in the kernel files, as
> kernel developers don't have to have the burden of checking if tooling
> continues to work when they change kernel files.
Always nice to have less work. :-)
> That way later the perf developers get the warning in the perf build
> process, see how this change in a file that is a copy from the kernel
> sources affects tooling, and act upon it, simply updating the copy or
> doing that + extra tooling adjustments, perhaps a new feature, etc.
Nice.
> Acked-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Thanks, queueing.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-22 15:15 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-21 6:33 linux-next: build failure after merge of the tip tree Stephen Rothwell
2020-06-21 10:53 ` Borislav Petkov
2020-06-22 1:38 ` Stephen Rothwell
2020-06-22 13:04 ` [PATCH -v2] x86/msr: Move the F15h MSRs where they belong Borislav Petkov
2020-06-22 14:17 ` Arnaldo Carvalho de Melo
2020-06-22 15:15 ` Borislav Petkov
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