From: Christoph Hellwig <hch@lst.de>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: sagi@grimberg.me, Ilias Apalodimas <ilias.apalodimas@linaro.org>,
linux-nvme@lists.infradead.org, axboe@fb.com,
Keith Busch <kbusch@kernel.org>, Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v3] nvme: retain split access workaround for capability reads
Date: Mon, 7 Oct 2019 14:47:02 +0200 [thread overview]
Message-ID: <20191007124702.GA28611@lst.de> (raw)
In-Reply-To: <CAKv+Gu8cyR6Wcp4bSy4iDs0ALfzvOBwNmqx-_SbiPwwSGSFZVA@mail.gmail.com>
On Mon, Oct 07, 2019 at 02:32:43PM +0200, Ard Biesheuvel wrote:
> OK, that is good to know. Mind you, I used 'interconnect' in the
> abstract sense, meaning whatever sits between the CPU doing the read
> and the 64-bit register in the BAR space.
>
> But I fail to see your point. Why is it relevant for deciding whether
> to apply a NVMe fix if the affected hardware can or cannot use other
> types of PCIe devices? Note that I am not proposing some hacky
> workaround to be applied, but just to stick with the workaround that
> was already accepted (and I'm pretty sure that this Apple hardware got
> broken too with commit 7fd8930f26be4)
That isn't the point. I'm fine with the technical changes, but the
commit log and the comment seem to imply that this fixes your
interconnect issue. It does not - at best it works around it for this
particular device, and even that only as a side effet for fixing a device
side bug.
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next prev parent reply other threads:[~2019-10-07 12:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-07 11:42 [PATCH v3] nvme: retain split access workaround for capability reads Ard Biesheuvel
2019-10-07 12:07 ` Christoph Hellwig
2019-10-07 12:24 ` Ard Biesheuvel
2019-10-07 12:27 ` Christoph Hellwig
2019-10-07 12:32 ` Ard Biesheuvel
2019-10-07 12:47 ` Christoph Hellwig [this message]
2019-10-07 12:48 ` Keith Busch
2019-10-07 13:20 ` Ard Biesheuvel
2019-10-07 13:32 ` Keith Busch
2019-10-07 13:33 ` Ard Biesheuvel
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