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From: Suman Anna <s-anna@ti.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>,
	<tglx@linutronix.de>, <jason@lakedaemon.net>,
	<robh+dt@kernel.org>, <lee.jones@linaro.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <david@lechnology.com>,
	<wmills@ti.com>
Subject: Re: [PATCHv3 3/6] irqchip/irq-pruss-intc: Add support for shared and invalid interrupts
Date: Sat, 25 Jul 2020 10:57:00 -0500
Message-ID: <14a0978a-f38f-8cd7-3fee-b0e438513396@ti.com> (raw)
In-Reply-To: <87imemxv3l.wl-maz@kernel.org>

Hi Marc,

On 7/17/20 6:02 AM, Marc Zyngier wrote:
> On Fri, 10 Jul 2020 21:59:17 +0100,
> Suman Anna <s-anna@ti.com> wrote:
> 
> Hi Suman,
> 
> [...]
> 
>>
>> Hi Marc,
>>
>> On 7/2/20 12:44 PM, Marc Zyngier wrote:
>>> On 2020-07-02 15:17, Grzegorz Jaszczyk wrote:
>>>> From: Suman Anna <s-anna@ti.com>
>>>>
>>>> The PRUSS INTC has a fixed number of output interrupt lines that are
>>>> connected to a number of processors or other PRUSS instances or other
>>>> devices (like DMA) on the SoC. The output interrupt lines 2 through 9
>>>> are usually connected to the main Arm host processor and are referred
>>>> to as host interrupts 0 through 7 from ARM/MPU perspective.
>>>>
>>>> All of these 8 host interrupts are not always exclusively connected
>>>> to the Arm interrupt controller. Some SoCs have some interrupt lines
>>>> not connected to the Arm interrupt controller at all, while a few others
>>>> have the interrupt lines connected to multiple processors in which they
>>>> need to be partitioned as per SoC integration needs. For example, AM437x
>>>> and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5
>>>> connected to the other PRUSS, while AM335x has host interrupt 0 shared
>>>> between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and
>>>> a DMA controller.
>>>>
>>>> Add support to the PRUSS INTC driver to allow both these shared and
>>>> invalid interrupts by not returning a failure if any of these interrupts
>>>> are skipped from the corresponding INTC DT node.
>>>
>>> That's not exactly "adding support", is it? It really is "ignore these
>>> interrupts because they are useless from the main CPU's perspective",
>>> right?
>>
>> Correct. We can rephrase this to something like
>> "Add logic to the PRUSS INTC driver to ignore.."
>>
>>>
>>>>
>>>> Signed-off-by: Suman Anna <s-anna@ti.com>
>>>> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
>>>> ---
>>>> v2->v3:
>>>> - Extra checks for (intc->irqs[i]) in error/remove path was moved from
>>>>    "irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS
>>>>    interrupts" to this patch
>>>> v1->v2:
>>>> - https://patchwork.kernel.org/patch/11069757/
>>>> ---
>>>>   drivers/irqchip/irq-pruss-intc.c | 73
>>>> +++++++++++++++++++++++++++++++++++++---
>>>>   1 file changed, 68 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-pruss-intc.c
>>>> b/drivers/irqchip/irq-pruss-intc.c
>>>> index fb3dda3..49c936f 100644
>>>> --- a/drivers/irqchip/irq-pruss-intc.c
>>>> +++ b/drivers/irqchip/irq-pruss-intc.c
>>>> @@ -65,11 +65,15 @@
>>>>    * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
>>>>    * @base: base virtual address of INTC register space
>>>>    * @domain: irq domain for this interrupt controller
>>>> + * @shared_intr: bit-map denoting if the MPU host interrupt is shared
>>>
>>> nit: bitmap
>>
>> ok
>>
>>>
>>>> + * @invalid_intr: bit-map denoting if host interrupt is not
>>>> connected to MPU
>>>>    */
>>>>   struct pruss_intc {
>>>>       unsigned int irqs[MAX_NUM_HOST_IRQS];
>>>>       void __iomem *base;
>>>>       struct irq_domain *domain;
>>>> +    u16 shared_intr;
>>>> +    u16 invalid_intr;
>>>
>>> Please represent bitmaps as an unsigned long.
>>
>> ok. We have atmost 8 interrupts coming in, but agree on the change
>> since we are using the BIT() macro below.
>>
>>>
>>>>   };
>>>>
>>>>   static inline u32 pruss_intc_read_reg(struct pruss_intc *intc,
>>>> unsigned int reg)
>>>> @@ -222,7 +226,8 @@ static int pruss_intc_probe(struct
>>>> platform_device *pdev)
>>>>           "host_intr4", "host_intr5", "host_intr6", "host_intr7", };
>>>>       struct device *dev = &pdev->dev;
>>>>       struct pruss_intc *intc;
>>>> -    int i, irq;
>>>> +    int i, irq, count;
>>>> +    u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
>>>>
>>>>       intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
>>>>       if (!intc)
>>>> @@ -235,6 +240,52 @@ static int pruss_intc_probe(struct
>>>> platform_device *pdev)
>>>>           return PTR_ERR(intc->base);
>>>>       }
>>>>
>>>> +    count = of_property_read_variable_u8_array(dev->of_node,
>>>> +                           "ti,irqs-reserved",
>>>> +                           temp_intr, 0,
>>>> +                           MAX_NUM_HOST_IRQS);
>>>> +    /*
>>>> +     * The irqs-reserved is used only for some SoC's therefore not
>>>> having
>>>> +     * this property is still valid
>>>> +     */
>>>> +    if (count == -EINVAL)
>>>> +        count = 0;
>>>> +    if (count < 0)
>>>> +        return count;
>>>> +
>>>> +    for (i = 0; i < count; i++) {
>>>> +        if (temp_intr[i] >= MAX_NUM_HOST_IRQS) {
>>>> +            dev_warn(dev, "ignoring invalid reserved irq %d\n",
>>>> +                 temp_intr[i]);
>>>> +            continue;
>>>> +        }
>>>> +
>>>> +        intc->invalid_intr |= BIT(temp_intr[i]);
>>>> +    }
>>>> +
>>>> +    count = of_property_read_variable_u8_array(dev->of_node,
>>>> +                           "ti,irqs-shared",
>>>> +                           temp_intr, 0,
>>>> +                           MAX_NUM_HOST_IRQS);
>>>> +    /*
>>>> +     * The irqs-shared is used only for some SoC's therefore not having
>>>> +     * this property is still valid
>>>> +     */
>>>> +    if (count == -EINVAL)
>>>> +        count = 0;
>>>> +    if (count < 0)
>>>> +        return count;
>>>> +
>>>> +    for (i = 0; i < count; i++) {
>>>> +        if (temp_intr[i] >= MAX_NUM_HOST_IRQS) {
>>>> +            dev_warn(dev, "ignoring invalid shared irq %d\n",
>>>> +                 temp_intr[i]);
>>>> +            continue;
>>>> +        }
>>>> +
>>>> +        intc->shared_intr |= BIT(temp_intr[i]);
>>>> +    }
>>>> +
>>>
>>> You probably want to move this in a separate function, since you populate a
>>> common structure.
>>>
>>>>       pruss_intc_init(intc);
>>>>
>>>>       /* always 64 events */
>>>> @@ -244,8 +295,14 @@ static int pruss_intc_probe(struct
>>>> platform_device *pdev)
>>>>           return -ENOMEM;
>>>>
>>>>       for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
>>>> +        if (intc->invalid_intr & BIT(i))
>>>> +            continue;
>>>> +
>>>>           irq = platform_get_irq_byname(pdev, irq_names[i]);
>>>>           if (irq <= 0) {
>>>> +            if (intc->shared_intr & BIT(i))
>>>> +                continue;
>>>
>>> I don't really understand why you are treating these "shared" interrupts
>>> differently from the invalid ones. In all cases, they shouldn't be used.
>>
>> The behavior is the same in how we handle it, but the difference is
>> that an "invalid" one is never even connected to the ARM interrupt
>> controller, while the "shared" one is a choice. So, unless this
>> interrupt is being used/handled by a different processor/entity, you
>> would not see this skipped from the dts node.
> 
> And I'm saying that all that matters is that you are discarding these
> interrupts. Whether they are flagged invalid or shared, they are not
> available to Linux. So the difference in handling is pointless and
> only makes it harder to understand what you are doing.

The primary reason for using two properties and this logic was to 
accurately describe the h/w and usage of these in the DT bindings to 
distinguish the "never connected" vs the "optionally can be skipped" 
interrupts rather than go by how these are handled in the driver. I feel 
we will loose this description and make it confusing for SoC product 
integration developers.

Greg is planning to consolidate these for the next version. It would 
have been nice if we could have retained them.

regards
Suman

  reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-02 14:17 [PATCHv3 0/6] Add TI PRUSS Local Interrupt Controller IRQChip driver Grzegorz Jaszczyk
2020-07-02 14:17 ` [PATCHv3 1/6] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings Grzegorz Jaszczyk
2020-07-13 21:25   ` Rob Herring
2020-07-16  9:25     ` Grzegorz Jaszczyk
2020-07-02 14:17 ` [PATCHv3 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Grzegorz Jaszczyk
2020-07-02 17:24   ` Marc Zyngier
2020-07-03 14:28     ` Grzegorz Jaszczyk
2020-07-04  9:39       ` Marc Zyngier
2020-07-05 13:26         ` Grzegorz Jaszczyk
2020-07-05 20:45           ` Marc Zyngier
2020-07-08  7:04             ` Grzegorz Jaszczyk
2020-07-08 10:47               ` Marc Zyngier
2020-07-10 23:03                 ` Suman Anna
2020-07-15 13:38                   ` Grzegorz Jaszczyk
2020-07-17 12:36                     ` Marc Zyngier
2020-07-21  9:27                       ` Grzegorz Jaszczyk
2020-07-21 10:10                         ` Marc Zyngier
2020-07-21 13:59                           ` Grzegorz Jaszczyk
2020-07-02 14:17 ` [PATCHv3 3/6] irqchip/irq-pruss-intc: Add support for shared and invalid interrupts Grzegorz Jaszczyk
2020-07-02 17:44   ` Marc Zyngier
2020-07-10 20:59     ` Suman Anna
2020-07-17 11:02       ` Marc Zyngier
2020-07-25 15:57         ` Suman Anna [this message]
2020-07-25 16:27           ` Marc Zyngier
2020-07-25 16:39             ` Suman Anna
2020-07-02 14:17 ` [PATCHv3 4/6] irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk
2020-07-02 17:54   ` Marc Zyngier
2020-07-03 17:04     ` Grzegorz Jaszczyk
2020-07-10 21:04       ` Suman Anna
2020-07-02 14:17 ` [PATCHv3 5/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Grzegorz Jaszczyk
2020-07-02 17:59   ` Marc Zyngier
2020-07-03 17:05     ` Grzegorz Jaszczyk
2020-07-10 21:13       ` Suman Anna
2020-07-02 14:17 ` [PATCHv3 6/6] irqchip/irq-pruss-intc: Add event mapping support Grzegorz Jaszczyk
2020-07-02 16:24   ` Suman Anna
2020-07-05 13:39     ` Grzegorz Jaszczyk

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