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From: Tony Lindgren <tony@atomide.com>
To: Roger Quadros <rogerq@ti.com>
Cc: hch@lst.de, robin.murphy@arm.com, robh+dt@kernel.org, nm@ti.com,
	t-kristo@ti.com, nsekhar@ti.com, linux-omap@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	stable@kernel.org
Subject: Re: [PATCH] ARM: dts: omap5: Add bus_dma_limit for L3 bus
Date: Tue, 17 Mar 2020 10:01:40 -0700	[thread overview]
Message-ID: <20200317170140.GM37466@atomide.com> (raw)
In-Reply-To: <20200316102731.15467-1-rogerq@ti.com>

* Roger Quadros <rogerq@ti.com> [200316 03:28]:
> The L3 interconnect's memory map is from 0x0 to
> 0xffffffff. Out of this, System memory (SDRAM) can be
> accessed from 0x80000000 to 0xffffffff (2GB)
> 
> OMAP5 does support 4GB of SDRAM but upper 2GB can only be
> accessed by the MPU subsystem.
> 
> Add the dma-ranges property to reflect the physical address limit
> of the L3 bus.

Thanks applying into fixes.

Tony

      reply	other threads:[~2020-03-17 17:01 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-16 10:27 [PATCH] ARM: dts: omap5: Add bus_dma_limit for L3 bus Roger Quadros
2020-03-17 17:01 ` Tony Lindgren [this message]

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