[parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[Kyle McMartin]

The 16-byte alignment for ldcw doesn't seem to be required on PA2.0
processors (though the details of the insn in the manual are confusing)
so let's get rid of it.

This is a rather nice savings:
    text    data     bss     dec     hex filename
4020166 1814920  368896 6203982  5eaa4e vmlinux
4096278 1822416  373400 6292094  60027e vmlinux.orig

The comment on the PA2.0 case could use a little work though. :)

(I also added labels to the __SPIN_LOCK_UNLOCKED, as in the
 first pass through, I missed that, which caused very interesting
 build warnings...)

cheers,
	kyle

Index: include/asm-parisc/spinlock.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/spinlock.h,v
retrieving revision 1.10
diff -u -d -p -r1.10 spinlock.h
--- include/asm-parisc/spinlock.h	7 Mar 2005 15:05:48 -0000	1.10
+++ include/asm-parisc/spinlock.h	9 Jun 2005 04:23:03 -0000
@@ -10,7 +10,12 @@
 
 #ifndef CONFIG_DEBUG_SPINLOCK
 
-#define __SPIN_LOCK_UNLOCKED	{ { 1, 1, 1, 1 } }
+#ifdef CONFIG_PA20
+#define __SPIN_LOCK_UNLOCKED    { .lock = 1, }
+#else
+#define __SPIN_LOCK_UNLOCKED	{ .lock = { 1, 1, 1, 1 }, }
+#endif
+
 #undef SPIN_LOCK_UNLOCKED
 #define SPIN_LOCK_UNLOCKED (spinlock_t) __SPIN_LOCK_UNLOCKED
 
Index: include/asm-parisc/system.h
===================================================================
RCS file: /var/cvs/linux-2.6/include/asm-parisc/system.h,v
retrieving revision 1.11
diff -u -d -p -r1.11 system.h
--- include/asm-parisc/system.h	4 Jun 2005 07:11:25 -0000	1.11
+++ include/asm-parisc/system.h	9 Jun 2005 04:23:03 -0000
@@ -145,6 +145,7 @@ static inline void set_eiem(unsigned lon
 	__ret; \
 })
 
+#ifndef CONFIG_PA20
 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
    and GCC only guarantees 8-byte alignment for stack locals, we can't
    be assured of 16-byte alignment for atomic lock data even if we
@@ -152,6 +153,7 @@ static inline void set_eiem(unsigned lon
    we use a struct containing an array of four ints for the atomic lock
    type and dynamically select the 16-byte aligned int from the array
    for the semaphore.  */
+
 #define __PA_LDCW_ALIGNMENT 16
 #define __ldcw_align(a) ({ \
   unsigned long __ret = (unsigned long) &(a)->lock[0];        		\
@@ -159,13 +161,26 @@ static inline void set_eiem(unsigned lon
   (volatile unsigned int *) __ret;                                      \
 })
 
+#else /*CONFIG_PA20*/
+/* Apparently this architectural requirement was removed from PA2.0
+   processors. So we'll forego the 16-byte alignment on these machines. */
+
+#define __PA_LDCW_ALIGNMENT 4
+#define __ldcw_align(a) ((volatile unsigned int *)a)
+
+#endif /*!CONFIG_PA20*/
+
 #ifdef CONFIG_SMP
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
 
 typedef struct {
-	volatile unsigned int lock[4];
+#ifdef CONFIG_PA20
+	volatile unsigned int lock;
+#else
+        volatile unsigned int lock[4];
+#endif
 #ifdef CONFIG_DEBUG_SPINLOCK
 	unsigned long magic;
 	volatile unsigned int babble;

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Re: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[Grant Grundler]

On Thu, Jun 09, 2005 at 01:07:02AM -0400, Kyle McMartin wrote:
> The 16-byte alignment for ldcw doesn't seem to be required on PA2.0
> processors (though the details of the insn in the manual are confusing)

The PA 2.0 Arch book in fact requires it.

Jim Hull (HP PARISC/IPF Architect) published an errata later
indicating that the alignment could be relaxed to "native access"
(ie 4 byte for ldcw) if ",co" (Coherent Operation) completer was specified.
The email was dated Jan 29th, 2003.
But I can't a direct public reference of it. :^(

Just need to add ",co" to __ldcw() and we should be good.
That might need to be "ifdef CONFIG_PA20" as well...it's been
a while since we've had this conversion on parisc-linux mailing list.


> so let's get rid of it.
> 
> This is a rather nice savings:
>     text    data     bss     dec     hex filename
> 4020166 1814920  368896 6203982  5eaa4e vmlinux
> 4096278 1822416  373400 6292094  60027e vmlinux.orig

Nice indeed. :^)
I like the fact that we lose 76KB in code vs 7K+5K (data+bss).
Implies we might see a measurable perf increase in some code pathes.

> The comment on the PA2.0 case could use a little work though. :)
...
> --- include/asm-parisc/system.h	4 Jun 2005 07:11:25 -0000	1.11
> +++ include/asm-parisc/system.h	9 Jun 2005 04:23:03 -0000
...
> @@ -159,13 +161,26 @@ static inline void set_eiem(unsigned lon
>    (volatile unsigned int *) __ret;                                      \
>  })
>  
> +#else /*CONFIG_PA20*/
> +/* Apparently this architectural requirement was removed from PA2.0
> +   processors. So we'll forego the 16-byte alignment on these machines. */

You could borrow the comment from this patch:
http://lists.parisc-linux.org/pipermail/parisc-linux/2003-November/021747.html

Looks good to me. Please commit after fixing up the comment.

thanks,
grant
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Re: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[John David Anglin]

> Just need to add ",co" to __ldcw() and we should be good.
> That might need to be "ifdef CONFIG_PA20" as well...it's been
> a while since we've had this conversion on parisc-linux mailing list.

Yes, you need ",co" to get rid of the 16-byte alignment requirement.
This causes the operation to be done in cache which is a performance
win.  I think this is safe for SMP.  While the ",co" completer was
added in PA 1.1, it wasn't required that it be supported.  Thus,
I think we are stuck with 16-byte alignment on PA 1.1.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[Matthew Wilcox]

On Thu, Jun 09, 2005 at 10:29:24AM -0400, John David Anglin wrote:
> Yes, you need ",co" to get rid of the 16-byte alignment requirement.
> This causes the operation to be done in cache which is a performance
> win.  I think this is safe for SMP.  While the ",co" completer was
> added in PA 1.1, it wasn't required that it be supported.  Thus,
> I think we are stuck with 16-byte alignment on PA 1.1.

Agreed.  Fortunately, the only machines we care about that are both PA1.1
and SMP are the PA7200 based servers and workstations -- J200, J210, J210XC,
D250, D260, D350, D360, K100, K200, K210, K400 and K410.  Technically, the
early T-class servers and some G, H, I class servers were also SMP PA1.1,
but we don't really care about them.  Anyway, it seems pointless to penalise
the 64-bit machines for something that doesn't affect them.

For userspace, it's obviously different.  There, we have to cope with
any PA processor, and thus have to use a "self aligning" lock, but the
kernel can be fine tuned.

-- 
"Next the statesmen will invent cheap lies, putting the blame upon 
the nation that is attacked, and every man will be glad of those
conscience-soothing falsities, and will diligently study them, and refuse
to examine any refutations of them; and thus he will by and by convince 
himself that the war is just, and will thank God for the better sleep 
he enjoys after this process of grotesque self-deception." -- Mark Twain
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Re: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[Grant Grundler]

On Thu, Jun 09, 2005 at 03:46:15PM +0100, Matthew Wilcox wrote:
...
> For userspace, it's obviously different.  There, we have to cope with
> any PA processor, and thus have to use a "self aligning" lock, but the
> kernel can be fine tuned.

For *32-bit* userspace, I agree. Someday someone will be motivated
to get a 64-bit userspace together.

grant
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RE: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[Jim Hull]

Grant wrote: 

> Jim Hull (HP PARISC/IPF Architect) published an errata later
> indicating that the alignment could be relaxed to "native access"
> (ie 4 byte for ldcw) if ",co" (Coherent Operation) completer 
> was specified.
> The email was dated Jan 29th, 2003.
> But I can't a direct public reference of it. :^(

The public errata are here:

 
http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,592,0
0.html

and the semaphore alignment change is here:

 
http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,5310,
00.html

 -- Jim


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Re: [parisc-linux] Remove __ldcw_align for PA-RISC 2.0 processors

[John David Anglin]

> Grant wrote: 
> 
> > Jim Hull (HP PARISC/IPF Architect) published an errata later
> > indicating that the alignment could be relaxed to "native access"
> > (ie 4 byte for ldcw) if ",co" (Coherent Operation) completer 
> > was specified.
> > The email was dated Jan 29th, 2003.
> > But I can't a direct public reference of it. :^(

As an aside, binutils support for cache control completers was
recently improved for all load/store instructions.  Binutils
is now more precise in when cache control completers can be used.
It should now be possible to use either 1.x or 2.0 mnemonics
with cache control completers.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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