Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe
@ 2019-11-07  0:16 Bjorn Andersson
  2019-11-07  0:16 ` [PATCH v3 1/2] dt-bindings: " Bjorn Andersson
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-11-07  0:16 UTC (permalink / raw)
  To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi,
	Andrew Murray, Philipp Zabel
  Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel

This adds support necessary for the two PCIe controllers found in Qualcomm
SDM845.

Bjorn Andersson (2):
  dt-bindings: PCI: qcom: Add support for SDM845 PCIe
  PCI: qcom: Add support for SDM845 PCIe controller

 .../devicetree/bindings/pci/qcom,pcie.txt     |  19 +++
 drivers/pci/controller/dwc/pcie-qcom.c        | 150 ++++++++++++++++++
 2 files changed, 169 insertions(+)

-- 
2.23.0


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3 1/2] dt-bindings: PCI: qcom: Add support for SDM845 PCIe
  2019-11-07  0:16 [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson
@ 2019-11-07  0:16 ` " Bjorn Andersson
  2019-11-07  0:16 ` [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson
  2019-11-07 15:21 ` [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Julien Massot
  2 siblings, 0 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-11-07  0:16 UTC (permalink / raw)
  To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi,
	Andrew Murray, Philipp Zabel
  Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Rob Herring,
	Vinod Koul

Add compatible and necessary clocks and resets definitions for the
SDM845 PCIe controller.

Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

Changes since v1:
- Picked up Rob and Vinod's R-b

 .../devicetree/bindings/pci/qcom,pcie.txt     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index ada80b01bf0c..981b4de12807 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -11,6 +11,7 @@
 			- "qcom,pcie-ipq4019" for ipq4019
 			- "qcom,pcie-ipq8074" for ipq8074
 			- "qcom,pcie-qcs404" for qcs404
+			- "qcom,pcie-sdm845" for sdm845
 
 - reg:
 	Usage: required
@@ -126,6 +127,18 @@
 			- "master_bus"	AXI Master clock
 			- "slave_bus"	AXI Slave clock
 
+-clock-names:
+	Usage: required for sdm845
+	Value type: <stringlist>
+	Definition: Should contain the following entries
+			- "aux"		Auxiliary clock
+			- "cfg"		Configuration clock
+			- "bus_master"	Master AXI clock
+			- "bus_slave"	Slave AXI clock
+			- "slave_q2a"	Slave Q2A clock
+			- "tbu"		PCIe TBU clock
+			- "pipe"	PIPE clock
+
 - resets:
 	Usage: required
 	Value type: <prop-encoded-array>
@@ -188,6 +201,12 @@
 			- "pwr"			PWR reset
 			- "ahb"			AHB reset
 
+- reset-names:
+	Usage: required for sdm845
+	Value type: <stringlist>
+	Definition: Should contain the following entries
+			- "pci"			PCIe core reset
+
 - power-domains:
 	Usage: required for apq8084 and msm8996/apq8096
 	Value type: <prop-encoded-array>
-- 
2.23.0


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller
  2019-11-07  0:16 [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson
  2019-11-07  0:16 ` [PATCH v3 1/2] dt-bindings: " Bjorn Andersson
@ 2019-11-07  0:16 ` Bjorn Andersson
  2019-11-07 13:38   ` Philipp Zabel
  2019-11-13 12:47   ` Stanimir Varbanov
  2019-11-07 15:21 ` [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Julien Massot
  2 siblings, 2 replies; 6+ messages in thread
From: Bjorn Andersson @ 2019-11-07  0:16 UTC (permalink / raw)
  To: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi,
	Andrew Murray, Philipp Zabel
  Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Vinod Koul

The SDM845 has one Gen2 and one Gen3 controller, add support for these.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

Changes since v1:
- Don't assert the reset in the failure path

 drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++++++++
 1 file changed, 150 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7e581748ee9f..5ea527a6bd9f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -54,6 +54,7 @@
 #define PCIE20_PARF_LTSSM			0x1B0
 #define PCIE20_PARF_SID_OFFSET			0x234
 #define PCIE20_PARF_BDF_TRANSLATE_CFG		0x24C
+#define PCIE20_PARF_DEVICE_TYPE			0x1000
 
 #define PCIE20_ELBI_SYS_CTRL			0x04
 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE		BIT(0)
@@ -80,6 +81,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define DEVICE_TYPE_RC				0x4
+
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
 struct qcom_pcie_resources_2_1_0 {
 	struct clk *iface_clk;
@@ -139,12 +142,20 @@ struct qcom_pcie_resources_2_3_3 {
 	struct reset_control *rst[7];
 };
 
+struct qcom_pcie_resources_2_7_0 {
+	struct clk_bulk_data clks[6];
+	struct regulator_bulk_data supplies[2];
+	struct reset_control *pci_reset;
+	struct clk *pipe_clk;
+};
+
 union qcom_pcie_resources {
 	struct qcom_pcie_resources_1_0_0 v1_0_0;
 	struct qcom_pcie_resources_2_1_0 v2_1_0;
 	struct qcom_pcie_resources_2_3_2 v2_3_2;
 	struct qcom_pcie_resources_2_3_3 v2_3_3;
 	struct qcom_pcie_resources_2_4_0 v2_4_0;
+	struct qcom_pcie_resources_2_7_0 v2_7_0;
 };
 
 struct qcom_pcie;
@@ -1068,6 +1079,134 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 	return ret;
 }
 
+static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+	int ret;
+
+	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
+	if (IS_ERR(res->pci_reset))
+		return PTR_ERR(res->pci_reset);
+
+	res->supplies[0].supply = "vdda";
+	res->supplies[1].supply = "vddpe-3v3";
+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
+				      res->supplies);
+	if (ret)
+		return ret;
+
+	res->clks[0].id = "aux";
+	res->clks[1].id = "cfg";
+	res->clks[2].id = "bus_master";
+	res->clks[3].id = "bus_slave";
+	res->clks[4].id = "slave_q2a";
+	res->clks[5].id = "tbu";
+
+	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+	if (ret < 0)
+		return ret;
+
+	res->pipe_clk = devm_clk_get(dev, "pipe");
+	return PTR_ERR_OR_ZERO(res->pipe_clk);
+}
+
+static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+	u32 val;
+	int ret;
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
+	if (ret < 0) {
+		dev_err(dev, "cannot enable regulators\n");
+		return ret;
+	}
+
+	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+	if (ret < 0)
+		goto err_disable_regulators;
+
+	ret = reset_control_assert(res->pci_reset);
+	if (ret < 0) {
+		dev_err(dev, "cannot deassert pci reset\n");
+		goto err_disable_clocks;
+	}
+
+	usleep_range(1000, 1500);
+
+	ret = reset_control_deassert(res->pci_reset);
+	if (ret < 0) {
+		dev_err(dev, "cannot deassert pci reset\n");
+		goto err_disable_clocks;
+	}
+
+	ret = clk_prepare_enable(res->pipe_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable pipe clock\n");
+		goto err_disable_clocks;
+	}
+
+	/* configure PCIe to RC mode */
+	writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+
+	/* enable PCIe clocks and resets */
+	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+	val &= ~BIT(0);
+	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+	/* change DBI base address */
+	writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+	/* MAC PHY_POWERDOWN MUX DISABLE  */
+	val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
+	val &= ~BIT(29);
+	writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+	val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+	val |= BIT(4);
+	writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+		val |= BIT(31);
+		writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+	}
+
+	return 0;
+err_disable_clocks:
+	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+err_disable_regulators:
+	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
+
+	return ret;
+}
+
+static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+
+	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
+}
+
+static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+
+	return clk_prepare_enable(res->pipe_clk);
+}
+
+static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
+{
+	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+
+	clk_disable_unprepare(res->pipe_clk);
+}
+
 static int qcom_pcie_link_up(struct dw_pcie *pci)
 {
 	u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
@@ -1167,6 +1306,16 @@ static const struct qcom_pcie_ops ops_2_3_3 = {
 	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
 };
 
+/* Qcom IP rev.: 2.7.0	Synopsys IP rev.: 4.30a */
+static const struct qcom_pcie_ops ops_2_7_0 = {
+	.get_resources = qcom_pcie_get_resources_2_7_0,
+	.init = qcom_pcie_init_2_7_0,
+	.deinit = qcom_pcie_deinit_2_7_0,
+	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+	.post_init = qcom_pcie_post_init_2_7_0,
+	.post_deinit = qcom_pcie_post_deinit_2_7_0,
+};
+
 static const struct dw_pcie_ops dw_pcie_ops = {
 	.link_up = qcom_pcie_link_up,
 };
@@ -1282,6 +1431,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
+	{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
 	{ }
 };
 
-- 
2.23.0


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller
  2019-11-07  0:16 ` [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson
@ 2019-11-07 13:38   ` Philipp Zabel
  2019-11-13 12:47   ` Stanimir Varbanov
  1 sibling, 0 replies; 6+ messages in thread
From: Philipp Zabel @ 2019-11-07 13:38 UTC (permalink / raw)
  To: Bjorn Andersson, Bjorn Helgaas, Stanimir Varbanov,
	Lorenzo Pieralisi, Andrew Murray
  Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Vinod Koul

On Wed, 2019-11-06 at 16:16 -0800, Bjorn Andersson wrote:
> The SDM845 has one Gen2 and one Gen3 controller, add support for these.
> 
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe
  2019-11-07  0:16 [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson
  2019-11-07  0:16 ` [PATCH v3 1/2] dt-bindings: " Bjorn Andersson
  2019-11-07  0:16 ` [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson
@ 2019-11-07 15:21 ` Julien Massot
  2 siblings, 0 replies; 6+ messages in thread
From: Julien Massot @ 2019-11-07 15:21 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Bjorn Helgaas, Stanimir Varbanov, Lorenzo Pieralisi,
	Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
	devicetree, linux-kernel

Hi Bjorn,

On Thu, Nov 7, 2019 at 1:16 AM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> This adds support necessary for the two PCIe controllers found in Qualcomm
> SDM845.

Thanks a lot the gen 3 PCIE works on my 845 platform.
Tested-by: Julien Massot <jmassot@softbankrobotics.com>

-- 


*This email and any attachment thereto are confidential and intended 
solely for the use of the individual or entity to whom they are addressed.

If you are not the intended recipient, please be advised that disclosing, 
copying, distributing or taking any action in reliance on the contents of 
this email is strictly prohibited. In such case, please immediately advise 
the sender, and delete all copies and attachment from your system.
This 
email shall not be construed and is not tantamount to an offer, an 
acceptance of offer, or an agreement by SoftBank Robotics Europe on any 
discussion or contractual document whatsoever. No employee or agent is 
authorized to represent or bind SoftBank Robotics Europe to third parties 
by email, or act on behalf of SoftBank Robotics Europe by email, without 
express written confirmation by SoftBank Robotics Europe’ duly authorized 
representatives.
*



*Ce message électronique et éventuelles pièces 
jointes sont confidentiels, et exclusivement destinés à la personne ou 
l'entité à qui ils sont adressés.
Si vous n'êtes pas le destinataire visé, 
vous êtes prié de ne pas divulguer, copier, distribuer ou prendre toute 
décision sur la foi de ce message électronique. Merci d'en aviser 
immédiatement l'expéditeur et de supprimer toutes les copies et éventuelles 
pièces jointes de votre système.
Ce message électronique n'équivaut pas à 
une offre, à une acceptation d’offre, ou à un accord de SoftBank Robotics 
Europe sur toute discussion ou document contractuel quel qu’il soit, et ne 
peut être interprété comme tel. Aucun employé ou agent de SoftBank Robotics 
Europe n'est autorisé à représenter ou à engager la société par email, ou à 
agir au nom et pour le compte de la société par email, sans qu’une 
confirmation écrite soit donnée par le représentant légal de SoftBank 
Robotics Europe ou par toute autre personne ayant reçu délégation de 
pouvoir appropriée.
*

**

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller
  2019-11-07  0:16 ` [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson
  2019-11-07 13:38   ` Philipp Zabel
@ 2019-11-13 12:47   ` Stanimir Varbanov
  1 sibling, 0 replies; 6+ messages in thread
From: Stanimir Varbanov @ 2019-11-13 12:47 UTC (permalink / raw)
  To: Bjorn Andersson, Bjorn Helgaas, Lorenzo Pieralisi, Andrew Murray,
	Philipp Zabel
  Cc: linux-arm-msm, linux-pci, devicetree, linux-kernel, Vinod Koul


On 11/7/19 2:16 AM, Bjorn Andersson wrote:
> The SDM845 has one Gen2 and one Gen3 controller, add support for these.
> 
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
> 
> Changes since v1:
> - Don't assert the reset in the failure path
> 
>  drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++++++++
>  1 file changed, 150 insertions(+)

Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

-- 
regards,
Stan

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, back to index

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-07  0:16 [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Bjorn Andersson
2019-11-07  0:16 ` [PATCH v3 1/2] dt-bindings: " Bjorn Andersson
2019-11-07  0:16 ` [PATCH v3 2/2] PCI: qcom: Add support for SDM845 PCIe controller Bjorn Andersson
2019-11-07 13:38   ` Philipp Zabel
2019-11-13 12:47   ` Stanimir Varbanov
2019-11-07 15:21 ` [PATCH v3 0/2] PCI: qcom: Add support for SDM845 PCIe Julien Massot

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org
	public-inbox-index linux-pci

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git