From: Jiang Liu <liuj97@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>, Don Dutile <ddutile@redhat.com>
Cc: Yijing Wang <wangyijing@huawei.com>,
Yinghai Lu <yinghai@kernel.org>,
Taku Izumi <izumi.taku@jp.fujitsu.com>,
"Rafael J . Wysocki" <rjw@sisk.pl>,
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Jiang Liu <liuj97@gmail.com>
Subject: [PATCH v3 01/32] PCI: add pcie_flags_reg into struct pci_dev to cache PCIe capabilities register
Date: Wed, 1 Aug 2012 23:54:06 +0800 [thread overview]
Message-ID: <1343836477-7287-2-git-send-email-jiang.liu@huawei.com> (raw)
In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
From: Yijing Wang <wangyijing@huawei.com>
From: Yijing Wang <wangyijing@huawei.com>
Since PCI Express Capabilities Register is read only, cache its value
into struct pci_dev to avoid repeatedly calling pci_read_config_*().
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
---
drivers/pci/probe.c | 3 ++-
include/linux/pci.h | 10 ++++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 6c143b4..ba4d855 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -929,7 +929,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
pdev->is_pcie = 1;
pdev->pcie_cap = pos;
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
- pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
+ pdev->pcie_flags_reg = reg16;
+ pdev->pcie_type = pci_pcie_type(pdev);
pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5faa831..95662b2 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -258,6 +258,7 @@ struct pci_dev {
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
u8 rom_base_reg; /* which config register controls the ROM */
u8 pin; /* which interrupt pin this device uses */
+ u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
struct pci_driver *driver; /* which driver has allocated this device */
u64 dma_mask; /* Mask of the bits of bus address this
@@ -1650,6 +1651,15 @@ static inline bool pci_is_pcie(struct pci_dev *dev)
return !!pci_pcie_cap(dev);
}
+/**
+ * pci_pcie_type - get the PCIe device/port type
+ * @dev: PCI device
+ */
+static inline int pci_pcie_type(const struct pci_dev *dev)
+{
+ return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
+}
+
void pci_request_acs(void);
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
bool pci_acs_path_enabled(struct pci_dev *start,
--
1.7.9.5
next prev parent reply other threads:[~2012-08-01 15:54 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-01 15:54 [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Jiang Liu
2012-08-01 15:54 ` Jiang Liu [this message]
2012-08-01 15:54 ` [PATCH v3 02/32] PCI: introduce pci_pcie_type(dev) to replace pci_dev->pcie_type Jiang Liu
2012-08-01 15:54 ` [PATCH v3 03/32] PCI: remove unused field pcie_type from struct pci_dev Jiang Liu
2012-08-01 15:54 ` [PATCH v3 04/32] PCI: add PCIe capabilities access functions to hide differences among PCIe specs Jiang Liu
2012-08-01 15:54 ` [PATCH v3 05/32] PCI/core: use PCIe capabilities access functions to simplify implementation Jiang Liu
2012-08-01 15:54 ` [PATCH v3 06/32] PCI/hotplug: " Jiang Liu
2012-08-02 1:30 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 07/32] PCI/portdrv: " Jiang Liu
2012-08-02 1:33 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 08/32] PCI/pciehp: " Jiang Liu
2012-08-02 1:37 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 09/32] PCI/PME: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 10/32] PCI/AER: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 11/32] PCI/ASPM: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 12/32] PCI/ARM: " Jiang Liu
2012-08-01 17:20 ` Stephen Warren
2012-08-02 5:58 ` Thierry Reding
2012-08-03 18:05 ` Stephen Warren
2012-08-01 15:54 ` [PATCH v3 13/32] PCI/MIPS: " Jiang Liu
2012-08-13 21:40 ` David Daney
2012-08-01 15:54 ` [PATCH v3 14/32] PCI/tile: " Jiang Liu
2012-08-01 21:07 ` Chris Metcalf
2012-08-01 15:54 ` [PATCH v3 15/32] PCI/r8169: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 16/32] PCI/broadcom: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 17/32] PCI/igb: " Jiang Liu
2012-08-02 22:12 ` Jeff Kirsher
2012-08-01 15:54 ` [PATCH v3 18/32] PCI/vxge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 19/32] PCI/mlx4: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 20/32] PCI/niu: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 21/32] PCI/myri10ge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 22/32] PCI/chelsio: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 23/32] PCI/atl1c: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 24/32] PCI/ath9k: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 25/32] PCI/iwl: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 26/32] PCI/mthca: " Jiang Liu
2012-08-02 21:46 ` Roland Dreier
2012-08-01 15:54 ` [PATCH v3 27/32] PCI/qib: " Jiang Liu
2012-08-01 17:30 ` Marciniszyn, Mike
2012-08-01 15:54 ` [PATCH v3 28/32] PCI/qla: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 29/32] PCI/radeon: " Jiang Liu
2012-08-01 16:04 ` Deucher, Alexander
2012-08-01 15:54 ` [PATCH v3 30/32] PCI/tsi721: " Jiang Liu
2012-08-09 14:16 ` Bounine, Alexandre
2012-08-01 15:54 ` [PATCH v3 31/32] PCI/et131x: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 32/32] PCI/rtl8192e: " Jiang Liu
2012-08-14 4:25 ` [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Bjorn Helgaas
2012-08-14 15:46 ` Jiang Liu
2012-08-20 15:26 ` Jiang Liu
2012-08-20 15:35 ` Bjorn Helgaas
2012-08-20 15:47 ` Jiang Liu
2012-08-20 16:10 ` Bjorn Helgaas
2012-08-20 22:13 ` Bjorn Helgaas
2012-08-21 4:40 ` Cui, Dexuan
2012-08-22 16:28 ` Bjorn Helgaas
2012-08-23 1:00 ` Cui, Dexuan
2012-08-23 1:51 ` Don Dutile
2012-08-21 15:59 ` Jiang Liu
2012-08-22 17:08 ` Bjorn Helgaas
2012-08-24 18:52 ` Bjorn Helgaas
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