From: Zhou Wang <wangzhou1@hisilicon.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jg1.han@samsung.com>,
Pratyush Anand <pratyush.anand@gmail.com>,
Arnd Bergmann <arnd@arndb.de>, <fabrice.gasnier@st.com>,
Liviu Dudau <Liviu.Dudau@arm.com>
Cc: <linux-pci@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <gabriele.paoloni@huawei.com>,
<yuanzhichang@hisilicon.com>, <zhudacai@hisilicon.com>,
<zhangjukuo@huawei.com>, <qiuzhenfa@hisilicon.com>,
<liguozhu@hisilicon.com>, Zhou Wang <wangzhou1@hisilicon.com>
Subject: [PATCH v2 4/4] Documentation: DT: Add Hisilicon PCIe host binding
Date: Wed, 3 Jun 2015 16:35:42 +0800 [thread overview]
Message-ID: <1433320542-49576-5-git-send-email-wangzhou1@hisilicon.com> (raw)
In-Reply-To: <1433320542-49576-1-git-send-email-wangzhou1@hisilicon.com>
This patch adds related DTS binding document for Hisilicon PCIe host driver.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
new file mode 100644
index 0000000..6c9b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -0,0 +1,46 @@
+Hisilicon PCIe host bridge DT description
+
+Hisilicon PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible: Should contain "hisilicon,hip05-pcie".
+- reg: Should contain rc_dbi, subctrl, config registers location and length.
+- reg-names: Must include the following entries:
+ "rc_dbi": controller configuration registers;
+ "subctrl": whole PCIe hosts configuration registers;
+ "config": PCIe configuration space registers.
+- msi-parent: Should be its_pcie which is an its receiving MSI interrupts.
+- port-id: Should be 0, 1, 2 or 3.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if dma operations are coherent.
+
+Example:
+ pcie@0xb0080000 {
+ compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
+ reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>,
+ <0x220 0x00000000 0 0x2000>;
+ reg-names = "rc_dbi", "subctrl", "config";
+ bus-range = <0 15>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
+ num-lanes = <8>;
+ port-id = <1>;
+ #interrupts-cells = <1>;
+ interrupts-map-mask = <0xf800 0 0 7>;
+ interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
+ 0x0 0 0 2 &mbigen_pcie 2 11
+ 0x0 0 0 3 &mbigen_pcie 3 12
+ 0x0 0 0 4 &mbigen_pcie 4 13>;
+ status = "ok";
+ };
--
1.9.1
prev parent reply other threads:[~2015-06-03 8:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 8:35 [PATCH v2 0/4] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
2015-06-03 8:35 ` [PATCH v2 1/4] ARM/PCI: remove align_resource callback in pcibios_align_resource Zhou Wang
2015-06-04 13:18 ` James Morse
2015-06-05 3:53 ` Zhou Wang
2015-06-03 8:35 ` [PATCH v2 2/4] PCI: designware: Add ARM64 support Zhou Wang
2015-06-04 13:19 ` James Morse
2015-06-05 8:11 ` Zhou Wang
2015-06-09 11:15 ` Lorenzo Pieralisi
2015-06-10 13:35 ` Gabriele Paoloni
2015-06-11 5:44 ` Zhou Wang
2015-06-11 14:32 ` Gabriele Paoloni
2015-06-16 11:30 ` Zhou Wang
2015-06-16 14:14 ` Gabriele Paoloni
2015-07-13 10:58 ` Lorenzo Pieralisi
2015-07-13 11:45 ` Zhou Wang
2015-07-13 14:17 ` Lorenzo Pieralisi
2015-07-17 10:45 ` Gabriele Paoloni
2015-06-11 2:51 ` Zhou Wang
2015-06-11 2:44 ` Zhou Wang
2015-06-14 19:18 ` Pratyush Anand
2015-06-16 10:14 ` Zhou Wang
2015-06-03 8:35 ` [PATCH v2 3/4] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05 Zhou Wang
2015-06-04 13:23 ` James Morse
2015-06-05 8:13 ` Zhou Wang
2015-06-03 8:35 ` Zhou Wang [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1433320542-49576-5-git-send-email-wangzhou1@hisilicon.com \
--to=wangzhou1@hisilicon.com \
--cc=Liviu.Dudau@arm.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=fabrice.gasnier@st.com \
--cc=gabriele.paoloni@huawei.com \
--cc=jg1.han@samsung.com \
--cc=liguozhu@hisilicon.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=pratyush.anand@gmail.com \
--cc=qiuzhenfa@hisilicon.com \
--cc=yuanzhichang@hisilicon.com \
--cc=zhangjukuo@huawei.com \
--cc=zhudacai@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).