[PATCH v3 0/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05

[PATCH v3 0/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05

[Zhou Wang]

This patchset adds PCIe host support for Hisilicon Soc Hip05. The PCIe hosts
use PCIe IP core from Synopsys, So this driver is base on designware PCIe driver.

Hip05 is an ARMv8 architecture Soc. It should be able to use ARM64 PCIe API in
designeware PCIe driver. So this patch also adds ARM64 support for designware
pcie.

I tested this patchset on D02 board of Hisilicon with Intel 82599 networking
card. It works well.

This patchset is based on v4.1-rc8.

Change from v2:
- move struct pci_dev *dev and struct pci_sys_data *sys in
  pcibios_align_resource in 1/5.
- Add Gabriele's codes in 2/5 which delete unnecessary information parse and
  use of_pci_get_host_bridge_resources for both ARM32 and ARM64.
- Add maintainer patch 5/5.

Change from RFC v1:
- Add 1/4 patch by Arnd which removes align_resource callback in ARM
  pcibios_align_resource.
- Change head file in pcie-designware from asm/hardirq.h to linux/hardirq.h.
- Set pp->root_bus_nr = 0 in dra7xx, exynos, imx6, keystone, layerscape,
  spear13xx.
- Remove unnecessary parentheses of some macros in pcie-hisi.
- Use macro to replace some magic values.
- Merge two loops together and add some comments about it in context_config
  function in pcie-hisi.
- Modify some value of items in pcie node example in binding document. 

Change from RFC:
- delete dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
  merge related operations into dw_pcie_host_init.

Link of v2:
- http://www.spinics.net/lists/linux-pci/msg41844.html
Link of RFC v1:
- http://www.spinics.net/lists/linux-pci/msg41305.html
Link of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html

Zhou Wang (5):
  ARM/PCI: remove align_resource callback in pcibios_align_resource
  PCI: designware: Add ARM64 support
  PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05
  Documentation: DT: Add Hisilicon PCIe host binding
  MAINTAINERS: Add pcie-hisi maintainer

 .../devicetree/bindings/pci/hisilicon-pcie.txt     |  46 ++++
 MAINTAINERS                                        |   7 +
 arch/arm/kernel/bios32.c                           |   6 -
 drivers/pci/host/Kconfig                           |   5 +
 drivers/pci/host/Makefile                          |   1 +
 drivers/pci/host/pci-dra7xx.c                      |   1 +
 drivers/pci/host/pci-exynos.c                      |   2 +-
 drivers/pci/host/pci-imx6.c                        |   2 +-
 drivers/pci/host/pci-keystone-dw.c                 |   2 +-
 drivers/pci/host/pci-keystone.c                    |   2 +-
 drivers/pci/host/pci-layerscape.c                  |   2 +-
 drivers/pci/host/pci-mvebu.c                       |  47 ++--
 drivers/pci/host/pcie-designware.c                 | 242 ++++++++-----------
 drivers/pci/host/pcie-designware.h                 |  10 +-
 drivers/pci/host/pcie-hisi.c                       | 258 +++++++++++++++++++++
 drivers/pci/host/pcie-spear13xx.c                  |   2 +-
 drivers/pci/setup-res.c                            |  27 ++-
 include/linux/pci.h                                |   3 +
 18 files changed, 482 insertions(+), 183 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
 create mode 100644 drivers/pci/host/pcie-hisi.c

-- 
1.9.1

[PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Zhou Wang]

This patch had added by Arnd Bergmann during last reviewing of v1 patchset[1].

PCI core codes call pcibios_align_resource(). In ARM specific one, it will
dereference pci_sys_data and call sys->align_resource. If we try to unify ARM
and ARM64 PCIe API in pcie-designware. it will bring kernel crash when run into
this dereferencing.

However, in ARM there is only pci-mvebu which implements align_resource. So
add align_resource call back in pci_host_bridge structure and override
pcibios_align_resource with it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>

[1] http://www.spinics.net/lists/linux-pci/msg41671.html
---
 arch/arm/kernel/bios32.c     |  6 ------
 drivers/pci/host/pci-mvebu.c | 47 ++++++++++++++++++++++++++++----------------
 drivers/pci/setup-res.c      | 27 ++++++++++++++++++++-----
 include/linux/pci.h          |  3 +++
 4 files changed, 55 insertions(+), 28 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index fcbbbb1..b01189f 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -468,7 +468,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
 		sys->busnr   = busnr;
 		sys->swizzle = hw->swizzle;
 		sys->map_irq = hw->map_irq;
-		sys->align_resource = hw->align_resource;
 		INIT_LIST_HEAD(&sys->resources);
 
 		if (hw->private_data)
@@ -588,8 +587,6 @@ char * __init pcibios_setup(char *str)
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 				resource_size_t size, resource_size_t align)
 {
-	struct pci_dev *dev = data;
-	struct pci_sys_data *sys = dev->sysdata;
 	resource_size_t start = res->start;
 
 	if (res->flags & IORESOURCE_IO && start & 0x300)
@@ -597,9 +594,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 
 	start = (start + align - 1) & ~(align - 1);
 
-	if (sys->align_resource)
-		return sys->align_resource(dev, res, start, size, align);
-
 	return start;
 }
 
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index 1ab8635..155d05f 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -22,6 +22,8 @@
 #include <linux/of_pci.h>
 #include <linux/of_platform.h>
 
+#include "../pci.h" /* HACK to see pci_find_host_bridge */
+
 /*
  * PCIe unit register offsets.
  */
@@ -751,27 +753,20 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
 	return 1;
 }
 
-static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+static resource_size_t mvebu_pcie_align_resource(void *data,
+						 const struct resource *res,
+						 resource_size_t size,
+						 resource_size_t align)
 {
-	struct mvebu_pcie *pcie = sys_to_pcie(sys);
-	struct pci_bus *bus;
+	struct pci_dev *dev = data;
 
-	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
-				  &mvebu_pcie_ops, sys, &sys->resources);
-	if (!bus)
-		return NULL;
+	resource_size_t start = res->start;
 
-	pci_scan_child_bus(bus);
+	if (res->flags & IORESOURCE_IO && start & 0x300)
+		start = (start + 0x3ff) & ~0x3ff;
 
-	return bus;
-}
+	start = (start + align - 1) & ~(align - 1);
 
-static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
-						 const struct resource *res,
-						 resource_size_t start,
-						 resource_size_t size,
-						 resource_size_t align)
-{
 	if (dev->bus->number != 0)
 		return start;
 
@@ -796,6 +791,25 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
 		return start;
 }
 
+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	struct mvebu_pcie *pcie = sys_to_pcie(sys);
+	struct pci_host_bridge *phb;
+	struct pci_bus *bus;
+
+	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
+				  &mvebu_pcie_ops, sys, &sys->resources);
+	if (!bus)
+		return NULL;
+
+	phb = pci_find_host_bridge(bus);
+	phb->align_resource = mvebu_pcie_align_resource;
+
+	pci_scan_child_bus(bus);
+
+	return bus;
+}
+
 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
 {
 	struct hw_pci hw;
@@ -812,7 +826,6 @@ static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
 	hw.scan           = mvebu_pcie_scan_bus;
 	hw.map_irq        = of_irq_parse_and_map_pci;
 	hw.ops            = &mvebu_pcie_ops;
-	hw.align_resource = mvebu_pcie_align_resource;
 
 	pci_common_init(&hw);
 }
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 232f925..73abca7 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -200,7 +200,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
 }
 
 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
-		int resno, resource_size_t size, resource_size_t align)
+		int resno, resource_size_t size, resource_size_t align,
+		resource_size_t (*alignf)(void *,
+					  const struct resource *,
+					  resource_size_t,
+					  resource_size_t))
 {
 	struct resource *res = dev->resource + resno;
 	resource_size_t min;
@@ -217,7 +221,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 	 */
 	ret = pci_bus_alloc_resource(bus, res, size, align, min,
 				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
-				     pcibios_align_resource, dev);
+				     alignf, dev);
 	if (ret == 0)
 		return 0;
 
@@ -229,7 +233,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
 		ret = pci_bus_alloc_resource(bus, res, size, align, min,
 					     IORESOURCE_PREFETCH,
-					     pcibios_align_resource, dev);
+					     alignf, dev);
 		if (ret == 0)
 			return 0;
 	}
@@ -242,7 +246,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 	 */
 	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
 		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
-					     pcibios_align_resource, dev);
+					     alignf, dev);
 
 	return ret;
 }
@@ -251,10 +255,23 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno,
 				resource_size_t size, resource_size_t min_align)
 {
 	struct pci_bus *bus;
+	struct pci_host_bridge *phb;
+	resource_size_t (*alignf)(void *,
+				  const struct resource *,
+				  resource_size_t,
+				  resource_size_t);
 	int ret;
 
 	bus = dev->bus;
-	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
+	phb = pci_find_host_bridge(bus);
+
+	if (phb->align_resource)
+		alignf = phb->align_resource;
+	else
+		alignf = pcibios_align_resource;
+
+	while ((ret = __pci_assign_resource(bus, dev, resno, size,
+					    min_align, alignf))) {
 		if (!bus->parent || !bus->self->transparent)
 			break;
 		bus = bus->parent;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 353db8d..39e48fc 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -404,6 +404,9 @@ struct pci_host_bridge {
 	struct device dev;
 	struct pci_bus *bus;		/* root bus */
 	struct list_head windows;	/* resource_entry */
+	resource_size_t (*align_resource)(void *data,
+			 const struct resource *res,
+			 resource_size_t size, resource_size_t align);
 	void (*release_fn)(struct pci_host_bridge *);
 	void *release_data;
 	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */
-- 
1.9.1

[PATCH v3 2/5] PCI: designware: Add ARM64 support

[Zhou Wang]

This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init. Also set pp->root_bus_nr = 0 in
each PCIe host driver which is based on pcie-designware. This patch also try
to use of_pci_get_host_bridge_resources for ARM32 and ARM64 according to the
suggestion for Gabriele[1]

I tested this patch on D02 board of Hisilicon. It works well.
I have compiled the driver with multi_v7_defconfig. However, I don't have
ARM32 PCIe related board to do test. It will be appreciated if someone could
help to test it.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Tested-by: James Morse <james.morse@arm.com>

[1] http://www.spinics.net/lists/linux-pci/msg42194.html
---
 drivers/pci/host/pci-dra7xx.c      |   1 +
 drivers/pci/host/pci-exynos.c      |   2 +-
 drivers/pci/host/pci-imx6.c        |   2 +-
 drivers/pci/host/pci-keystone-dw.c |   2 +-
 drivers/pci/host/pci-keystone.c    |   2 +-
 drivers/pci/host/pci-layerscape.c  |   2 +-
 drivers/pci/host/pcie-designware.c | 242 +++++++++++++++----------------------
 drivers/pci/host/pcie-designware.h |  10 +-
 drivers/pci/host/pcie-spear13xx.c  |   2 +-
 9 files changed, 110 insertions(+), 155 deletions(-)

diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 2d57e19..5c8b6ab 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -280,6 +280,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 
 	pp = &dra7xx->pp;
 	pp->dev = dev;
+	pp->root_bus_nr = 0;
 	pp->ops = &dra7xx_pcie_host_ops;
 
 	pp->irq = platform_get_irq(pdev, 1);
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c139237..4b6db6c 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -534,7 +534,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
 		}
 	}
 
-	pp->root_bus_nr = -1;
+	pp->root_bus_nr = 0;
 	pp->ops = &exynos_pcie_host_ops;
 
 	ret = dw_pcie_host_init(pp);
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index fdb9536..c4a80c5 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -541,7 +541,7 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
 		}
 	}
 
-	pp->root_bus_nr = -1;
+	pp->root_bus_nr = 0;
 	pp->ops = &imx6_pcie_host_ops;
 
 	ret = dw_pcie_host_init(pp);
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c
index f34892e..b1e4135 100644
--- a/drivers/pci/host/pci-keystone-dw.c
+++ b/drivers/pci/host/pci-keystone-dw.c
@@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
 {
 	struct pcie_port *pp = &ks_pcie->pp;
-	u32 start = pp->mem.start, end = pp->mem.end;
+	u32 start = pp->mem->start, end = pp->mem->end;
 	int i, tr_size;
 
 	/* Disable BARs for inbound access */
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index 75333b0..df91f5e 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -312,7 +312,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
 			return ret;
 	}
 
-	pp->root_bus_nr = -1;
+	pp->root_bus_nr = 0;
 	pp->ops = &keystone_pcie_host_ops;
 	ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
 	if (ret) {
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
index 4a6e62f..5c7a9c4 100644
--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
@@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie)
 	pp = &pcie->pp;
 	pp->dev = pcie->dev;
 	pp->dbi_base = pcie->dbi;
-	pp->root_bus_nr = -1;
+	pp->root_bus_nr = 0;
 	pp->ops = &ls_pcie_host_ops;
 
 	ret = dw_pcie_host_init(pp);
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e9f84f..844febee 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/hardirq.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
@@ -67,16 +68,7 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
-static struct hw_pci dw_pci;
-
-static unsigned long global_io_offset;
-
-static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
-	BUG_ON(!sys->private_data);
-
-	return sys->private_data;
-}
+static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
@@ -238,7 +230,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
 {
 	int irq, pos0, i;
-	struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
+	struct pcie_port *pp = desc->dev->bus->sysdata;
 
 	pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
 				       order_base_2(no_irqs));
@@ -281,7 +273,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
 {
 	int irq, pos;
 	struct msi_msg msg;
-	struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
+	struct pcie_port *pp = pdev->bus->sysdata;
 
 	if (desc->msi_attrib.is_msix)
 		return -EINVAL;
@@ -310,7 +302,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
 {
 	struct irq_data *data = irq_get_irq_data(irq);
 	struct msi_desc *msi = irq_data_get_msi(data);
-	struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
+	struct pcie_port *pp = msi->dev->bus->sysdata;
 
 	clear_irq_range(pp, irq, 1, data->hwirq);
 }
@@ -342,16 +334,24 @@ static const struct irq_domain_ops msi_domain_ops = {
 	.map = dw_pcie_msi_map,
 };
 
-int dw_pcie_host_init(struct pcie_port *pp)
+int __init dw_pcie_host_init(struct pcie_port *pp)
 {
 	struct device_node *np = pp->dev->of_node;
 	struct platform_device *pdev = to_platform_device(pp->dev);
-	struct of_pci_range range;
-	struct of_pci_range_parser parser;
+	struct pci_bus *bus;
 	struct resource *cfg_res;
+	LIST_HEAD(res);
 	u32 val, na, ns;
 	const __be32 *addrp;
 	int i, index, ret;
+	int rlen;
+	struct resource_entry *win;
+	const __be32 *parser_range_end = of_get_property(np, "ranges", &rlen);
+
+	if (parser_range_end == NULL)
+			return -ENOENT;
+	parser_range_end += rlen/sizeof(__be32);
+
 
 	/* Find the address cell size and the number of cells in order to get
 	 * the untranslated address.
@@ -375,78 +375,67 @@ int dw_pcie_host_init(struct pcie_port *pp)
 		dev_err(pp->dev, "missing *config* reg space\n");
 	}
 
-	if (of_pci_range_parser_init(&parser, np)) {
-		dev_err(pp->dev, "missing ranges property\n");
-		return -EINVAL;
-	}
+	ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
+	if (ret)
+		return ret;
 
 	/* Get the I/O and memory ranges from DT */
-	for_each_of_pci_range(&parser, &range) {
-		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-
-		if (restype == IORESOURCE_IO) {
-			of_pci_range_to_resource(&range, np, &pp->io);
-			pp->io.name = "I/O";
-			pp->io.start = max_t(resource_size_t,
-					     PCIBIOS_MIN_IO,
-					     range.pci_addr + global_io_offset);
-			pp->io.end = min_t(resource_size_t,
-					   IO_SPACE_LIMIT,
-					   range.pci_addr + range.size
-					   + global_io_offset - 1);
-			pp->io_size = resource_size(&pp->io);
-			pp->io_bus_addr = range.pci_addr;
-			pp->io_base = range.cpu_addr;
-
-			/* Find the untranslated IO space address */
-			pp->io_mod_base = of_read_number(parser.range -
-							 parser.np + na, ns);
-		}
-		if (restype == IORESOURCE_MEM) {
-			of_pci_range_to_resource(&range, np, &pp->mem);
-			pp->mem.name = "MEM";
-			pp->mem_size = resource_size(&pp->mem);
-			pp->mem_bus_addr = range.pci_addr;
-
-			/* Find the untranslated MEM space address */
-			pp->mem_mod_base = of_read_number(parser.range -
-							  parser.np + na, ns);
-		}
-		if (restype == 0) {
-			of_pci_range_to_resource(&range, np, &pp->cfg);
-			pp->cfg0_size = resource_size(&pp->cfg)/2;
-			pp->cfg1_size = resource_size(&pp->cfg)/2;
-			pp->cfg0_base = pp->cfg.start;
-			pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
+	resource_list_for_each_entry(win, &res) {
+		switch (resource_type(win->res)) {
+		case IORESOURCE_IO:
+			pp->io = win->res;
+			pp->io->name = "I/O";
+			pp->io_size = resource_size(pp->io);
+			pp->io_bus_addr = pp->io->start - win->offset;
+			/* magic 5 below comes from magic na and ns in
+			 * of_pci_range_parser_init()                 */
+			pp->io_mod_base = of_read_number(parser_range_end -
+					of_n_addr_cells(np) - 5 + na, ns);
+			ret = pci_remap_iospace(pp->io, pp->io_base);
+			if (ret) {
+				dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
+				ret, pp->io);
+			continue;
+			}
+			break;
+		case IORESOURCE_MEM:
+			pp->mem = win->res;
+			pp->mem->name = "MEM";
+			pp->mem_size = resource_size(pp->mem);
+			pp->mem_bus_addr = pp->mem->start - win->offset;
+			pp->mem_mod_base = of_read_number(parser_range_end -
+					of_n_addr_cells(np) - 5 + na, ns);
+			break;
+		case 0:
+			pp->cfg = win->res;
+			pp->cfg0_size = resource_size(pp->cfg)/2;
+			pp->cfg1_size = resource_size(pp->cfg)/2;
+			pp->cfg0_base = pp->cfg->start;
+			pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
 
 			/* Find the untranslated configuration space address */
-			pp->cfg0_mod_base = of_read_number(parser.range -
-							   parser.np + na, ns);
-			pp->cfg1_mod_base = pp->cfg0_mod_base +
-					    pp->cfg0_size;
+			pp->cfg0_mod_base = of_read_number(parser_range_end -
+					of_n_addr_cells(np) - 5 + na, ns);
+			pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
+			break;
+		case IORESOURCE_BUS:
+			pp->busn = win->res;
+			break;
+		default:
+			continue;
 		}
 	}
 
-	ret = of_pci_parse_bus_range(np, &pp->busn);
-	if (ret < 0) {
-		pp->busn.name = np->name;
-		pp->busn.start = 0;
-		pp->busn.end = 0xff;
-		pp->busn.flags = IORESOURCE_BUS;
-		dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
-			ret, &pp->busn);
-	}
-
 	if (!pp->dbi_base) {
-		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
-					resource_size(&pp->cfg));
+		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
+					resource_size(pp->cfg));
 		if (!pp->dbi_base) {
 			dev_err(pp->dev, "error with ioremap\n");
 			return -ENOMEM;
 		}
 	}
 
-	pp->mem_base = pp->mem.start;
+	pp->mem_base = pp->mem->start;
 
 	if (!pp->va_cfg0_base) {
 		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -493,24 +482,47 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	if (pp->ops->host_init)
 		pp->ops->host_init(pp);
 
-	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+	if (dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0)
+			!= PCIBIOS_SUCCESSFUL)
+		return -EINVAL;
 
 	/* program correct class for RC */
-	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+	if (dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI)
+			!= PCIBIOS_SUCCESSFUL)
+		return -EINVAL;
+
+	if (dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val)
+			!= PCIBIOS_SUCCESSFUL)
+		return -EINVAL;
 
-	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
-	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
 
-#ifdef CONFIG_PCI_MSI
-	dw_pcie_msi_chip.dev = pp->dev;
-	dw_pci.msi_ctrl = &dw_pcie_msi_chip;
+	if (dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val)
+			!= PCIBIOS_SUCCESSFUL)
+		return -EINVAL;
+
+	bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
+			      pp, &res);
+	if (!bus)
+		return -ENOMEM;
+
+#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
+	bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain);
+#else
+	bus->msi = &dw_pcie_msi_chip;
 #endif
 
-	dw_pci.nr_controllers = 1;
-	dw_pci.private_data = (void **)&pp;
+	pci_scan_child_bus(bus);
+	if (pp->ops->scan_bus)
+		pp->ops->scan_bus(pp);
 
-	pci_common_init_dev(pp->dev, &dw_pci);
+#ifdef CONFIG_ARM
+	/* support old dtbs that incorrectly describe IRQs */
+	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
+
+	pci_assign_unassigned_bus_resources(bus);
+	pci_bus_add_devices(bus);
 
 	return 0;
 }
@@ -653,7 +665,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp,
 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
-	struct pcie_port *pp = sys_to_pcie(bus->sysdata);
+	struct pcie_port *pp = bus->sysdata;
 	int ret;
 
 	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
@@ -677,7 +689,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
-	struct pcie_port *pp = sys_to_pcie(bus->sysdata);
+	struct pcie_port *pp = bus->sysdata;
 	int ret;
 
 	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
@@ -701,64 +713,6 @@ static struct pci_ops dw_pcie_ops = {
 	.write = dw_pcie_wr_conf,
 };
 
-static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-	struct pcie_port *pp;
-
-	pp = sys_to_pcie(sys);
-
-	if (global_io_offset < SZ_1M && pp->io_size > 0) {
-		sys->io_offset = global_io_offset - pp->io_bus_addr;
-		pci_ioremap_io(global_io_offset, pp->io_base);
-		global_io_offset += SZ_64K;
-		pci_add_resource_offset(&sys->resources, &pp->io,
-					sys->io_offset);
-	}
-
-	sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
-	pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
-	pci_add_resource(&sys->resources, &pp->busn);
-
-	return 1;
-}
-
-static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-	struct pci_bus *bus;
-	struct pcie_port *pp = sys_to_pcie(sys);
-
-	pp->root_bus_nr = sys->busnr;
-	bus = pci_create_root_bus(pp->dev, sys->busnr,
-				  &dw_pcie_ops, sys, &sys->resources);
-	if (!bus)
-		return NULL;
-
-	pci_scan_child_bus(bus);
-
-	if (bus && pp->ops->scan_bus)
-		pp->ops->scan_bus(pp);
-
-	return bus;
-}
-
-static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
-	int irq;
-
-	irq = of_irq_parse_and_map_pci(dev, slot, pin);
-	if (!irq)
-		irq = pp->irq;
-
-	return irq;
-}
-
-static struct hw_pci dw_pci = {
-	.setup		= dw_pcie_setup,
-	.scan		= dw_pcie_scan_bus,
-	.map_irq	= dw_pcie_map_irq,
-};
-
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
 	u32 val;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index d0bbd27..ab78710 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -34,7 +34,7 @@ struct pcie_port {
 	u64			cfg1_mod_base;
 	void __iomem		*va_cfg1_base;
 	u32			cfg1_size;
-	u64			io_base;
+	resource_size_t			io_base;
 	u64			io_mod_base;
 	phys_addr_t		io_bus_addr;
 	u32			io_size;
@@ -42,10 +42,10 @@ struct pcie_port {
 	u64			mem_mod_base;
 	phys_addr_t		mem_bus_addr;
 	u32			mem_size;
-	struct resource		cfg;
-	struct resource		io;
-	struct resource		mem;
-	struct resource		busn;
+	struct resource		*cfg;
+	struct resource		*io;
+	struct resource		*mem;
+	struct resource		*busn;
 	int			irq;
 	u32			lanes;
 	struct pcie_host_ops	*ops;
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index 020d788..e78ddf8 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -287,7 +287,7 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp,
 		return ret;
 	}
 
-	pp->root_bus_nr = -1;
+	pp->root_bus_nr = 0;
 	pp->ops = &spear13xx_pcie_host_ops;
 
 	ret = dw_pcie_host_init(pp);
-- 
1.9.1

[PATCH v3 3/5] PCI: hisi: Add PCIe host support for Hisilicon Soc Hip05

[Zhou Wang]

This patch adds PCIe host support for Hisilicon Soc Hip05.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
 drivers/pci/host/Kconfig     |   5 +
 drivers/pci/host/Makefile    |   1 +
 drivers/pci/host/pcie-hisi.c | 258 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 264 insertions(+)
 create mode 100644 drivers/pci/host/pcie-hisi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1dfb567..486d822 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -125,4 +125,9 @@ config PCIE_IPROC_PLATFORM
 	  Say Y here if you want to use the Broadcom iProc PCIe controller
 	  through the generic platform bus interface
 
+config PCI_HISI
+	depends on OF && ARM64
+	bool "Hisilicon Soc HIP05 PCIe controller"
+	select PCIE_DW
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index f733b4e..562142e 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
+obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
new file mode 100644
index 0000000..8328add
--- /dev/null
+++ b/drivers/pci/host/pcie-hisi.c
@@ -0,0 +1,258 @@
+/*
+ * PCIe host controller driver for Hisilicon Hip05 SoCs
+ *
+ * Copyright (C) 2015 Hisilicon Co., Ltd. http://www.hisilicon.com
+ *
+ * Author: Zhou Wang <wangzhou1@hisilicon.com>
+ *         Dacai Zhu <zhudacai@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_pci.h>
+#include <linux/platform_device.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_SUBCTRL_MODE_REG                           0x2800
+#define PCIE_SUBCTRL_SYS_STATE4_REG                     0x6818
+#define PCIE_SLV_DBI_MODE                               0x0
+#define PCIE_SLV_SYSCTRL_MODE                           0x1
+#define PCIE_SLV_CONTENT_MODE                           0x2
+#define PCIE_SLV_MSI_ASID                               0x10
+#define PCIE_LTSSM_LINKUP_STATE                         0x11
+#define PCIE_LTSSM_STATE_MASK                           0x3F
+#define PCIE_MSI_ASID_ENABLE                            (0x1 << 12)
+#define PCIE_MSI_ASID_VALUE                             (0x1 << 16)
+#define PCIE_MSI_TRANS_ENABLE                           (0x1 << 12)
+#define PCIE_MSI_TRANS_REG                              0x1c8
+#define PCIE_MSI_LOW_ADDRESS                            0x1b4
+#define PCIE_MSI_HIGH_ADDRESS                           0x1c4
+#define PCIE_MSI_ADDRESS_VAL                            0xb7010040
+
+#define to_hisi_pcie(x)	container_of(x, struct hisi_pcie, pp)
+
+struct hisi_pcie {
+	void __iomem *subctrl_base;
+	void __iomem *reg_base;
+	struct msi_controller *msi;
+	u32 port_id;
+	struct pcie_port pp;
+};
+
+static inline void hisi_pcie_subctrl_writel(struct hisi_pcie *pcie,
+					    u32 val, u32 reg)
+{
+	writel(val, pcie->subctrl_base + reg);
+}
+
+static inline u32 hisi_pcie_subctrl_readl(struct hisi_pcie *pcie, u32 reg)
+{
+	return readl(pcie->subctrl_base + reg);
+}
+
+static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
+					u32 val, u32 reg)
+{
+	writel(val, pcie->reg_base + reg);
+}
+
+static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
+{
+	return readl(pcie->reg_base + reg);
+}
+
+/*
+ * Change mode to indicate the same reg_base to base of PCIe host configure
+ * registers, base of RC configure space or base of vmid/asid context table
+ */
+static void hisi_pcie_change_apb_mode(struct hisi_pcie *pcie, u32 mode)
+{
+	u32 val;
+	u32 bit_mask;
+	u32 bit_shift;
+	u32 port_id = pcie->port_id;
+	u32 reg = PCIE_SUBCTRL_MODE_REG + 0x100 * port_id;
+
+	if ((port_id == 1) || (port_id == 2)) {
+		bit_mask = 0xc;
+		bit_shift = 0x2;
+	} else {
+		bit_mask = 0x6;
+		bit_shift = 0x1;
+	}
+
+	val = hisi_pcie_subctrl_readl(pcie, reg);
+	val = (val & (~bit_mask)) | (mode << bit_shift);
+	hisi_pcie_subctrl_writel(pcie, val, reg);
+}
+
+/* Configure vmid/asid table in PCIe host */
+static void hisi_pcie_config_context(struct hisi_pcie *pcie)
+{
+	int i;
+
+	hisi_pcie_change_apb_mode(pcie, PCIE_SLV_CONTENT_MODE);
+
+	/*
+	 * init vmid and asid tables for all PCIes device as 0
+	 * vmid table: 0 ~ 0x3ff, asid table: 0x400 ~ 0x7ff
+	 */
+	for (i = 0; i < 0x800; i++)
+		hisi_pcie_apb_writel(pcie, 0x0, i * 4);
+
+	hisi_pcie_change_apb_mode(pcie, PCIE_SLV_SYSCTRL_MODE);
+
+	hisi_pcie_apb_writel(pcie, PCIE_MSI_ADDRESS_VAL, PCIE_MSI_LOW_ADDRESS);
+	hisi_pcie_apb_writel(pcie, 0x0, PCIE_MSI_HIGH_ADDRESS);
+	hisi_pcie_apb_writel(pcie, PCIE_MSI_ASID_ENABLE | PCIE_MSI_ASID_VALUE,
+			     PCIE_SLV_MSI_ASID);
+	hisi_pcie_apb_writel(pcie, PCIE_MSI_TRANS_ENABLE, PCIE_MSI_TRANS_REG);
+
+	hisi_pcie_change_apb_mode(pcie, PCIE_SLV_DBI_MODE);
+}
+
+static int hisi_pcie_link_up(struct pcie_port *pp)
+{
+	u32 val;
+
+	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
+
+	val = hisi_pcie_subctrl_readl(hisi_pcie, PCIE_SUBCTRL_SYS_STATE4_REG +
+				      0x100 * hisi_pcie->port_id);
+
+	return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
+}
+
+static
+int hisi_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
+{
+	struct device_node *msi_node;
+	struct irq_domain *irq_domain;
+	struct device_node *np = pp->dev->of_node;
+	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
+
+	msi_node = of_parse_phandle(np, "msi-parent", 0);
+	if (!msi_node) {
+		pr_err("failed to find msi-parent\n");
+		return -ENODEV;
+	}
+
+	irq_domain = irq_find_host(msi_node);
+	if (!irq_domain) {
+		pr_err("failed to find irq domain\n");
+		return -ENODEV;
+	}
+
+	pp->irq_domain = irq_domain;
+
+	return 0;
+}
+
+static struct pcie_host_ops hisi_pcie_host_ops = {
+	.link_up = hisi_pcie_link_up,
+	.msi_host_init = hisi_pcie_msi_host_init,
+};
+
+static int __init hisi_add_pcie_port(struct pcie_port *pp,
+				     struct platform_device *pdev)
+{
+	int ret;
+	u32 port_id;
+	struct resource busn;
+
+	struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
+
+	if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) {
+		dev_err(&pdev->dev, "failed to read port-id\n");
+		return -EINVAL;
+	}
+	if (port_id > 3) {
+		dev_err(&pdev->dev, "Invalid port-id\n");
+		return -EINVAL;
+	}
+
+	hisi_pcie->port_id = port_id;
+
+	if (of_pci_parse_bus_range(pdev->dev.of_node, &busn)) {
+		dev_err(&pdev->dev, "failed to parse bus-ranges\n");
+		return -EINVAL;
+	}
+
+	pp->root_bus_nr = busn.start;
+	pp->ops = &hisi_pcie_host_ops;
+
+	hisi_pcie_config_context(hisi_pcie);
+
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __init hisi_pcie_probe(struct platform_device *pdev)
+{
+	struct hisi_pcie *hisi_pcie;
+	struct pcie_port *pp;
+	struct resource *reg;
+	struct resource *subctrl;
+	int ret;
+
+	hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL);
+	if (!hisi_pcie)
+		return -ENOMEM;
+
+	pp = &hisi_pcie->pp;
+	pp->dev = &pdev->dev;
+
+	subctrl = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subctrl");
+	hisi_pcie->subctrl_base = devm_ioremap_nocache(&pdev->dev,
+					subctrl->start, resource_size(subctrl));
+	if (IS_ERR(hisi_pcie->subctrl_base)) {
+		dev_err(pp->dev, "cannot get subctrl base\n");
+		return PTR_ERR(hisi_pcie->subctrl_base);
+	}
+
+	reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
+	hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg);
+	if (IS_ERR(hisi_pcie->reg_base)) {
+		dev_err(pp->dev, "cannot get reg base\n");
+		return PTR_ERR(hisi_pcie->reg_base);
+	}
+
+	hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
+
+	ret = hisi_add_pcie_port(pp, pdev);
+	if (ret < 0)
+		return ret;
+
+	platform_set_drvdata(pdev, hisi_pcie);
+
+	return ret;
+}
+
+static const struct of_device_id hisi_pcie_of_match[] = {
+	{.compatible = "hisilicon,hip05-pcie",},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, hisi_pcie_of_match);
+
+static struct platform_driver hisi_pcie_driver = {
+	.probe  = hisi_pcie_probe,
+	.driver = {
+		   .name = "hisi-pcie",
+		   .owner = THIS_MODULE,
+		   .of_match_table = hisi_pcie_of_match,
+	},
+};
+
+module_platform_driver(hisi_pcie_driver);
+
-- 
1.9.1

[PATCH v3 4/5] Documentation: DT: Add Hisilicon PCIe host binding

[Zhou Wang]

This patch adds related DTS binding document for Hisilicon PCIe host driver.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt     | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
new file mode 100644
index 0000000..6c9b827
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -0,0 +1,46 @@
+Hisilicon PCIe host bridge DT description
+
+Hisilicon PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible: Should contain "hisilicon,hip05-pcie".
+- reg: Should contain rc_dbi, subctrl, config registers location and length.
+- reg-names: Must include the following entries:
+  "rc_dbi": controller configuration registers;
+  "subctrl": whole PCIe hosts configuration registers;
+  "config": PCIe configuration space registers.
+- msi-parent: Should be its_pcie which is an its receiving MSI interrupts.
+- port-id: Should be 0, 1, 2 or 3.
+
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if dma operations are coherent.
+
+Example:
+	pcie@0xb0080000 {
+		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
+		reg = <0 0xb0080000 0 0x10000>, <0 0xb0000000 0 0x10000>,
+		      <0x220 0x00000000 0 0x2000>;
+		reg-names = "rc_dbi", "subctrl", "config";
+		bus-range = <0  15>;
+		msi-parent = <&its_pcie>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		dma-coherent;
+		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
+		num-lanes = <8>;
+		port-id = <1>;
+		#interrupts-cells = <1>;
+		interrupts-map-mask = <0xf800 0 0 7>;
+		interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
+				  0x0 0 0 2 &mbigen_pcie 2 11
+				  0x0 0 0 3 &mbigen_pcie 3 12
+				  0x0 0 0 4 &mbigen_pcie 4 13>;
+		status = "ok";
+	};
-- 
1.9.1

[PATCH v3 5/5] MAINTAINERS: Add pcie-hisi maintainer

[Zhou Wang]

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d8afd29..3f083d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7594,6 +7594,13 @@ L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/*spear*
 
+PCIE DRIVER FOR HISILICON
+M:	Zhou Wang <wangzhou1@hisilicon.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+F:	drivers/pci/host/pcie-hisi.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia@lists.infradead.org
-- 
1.9.1

RE: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Gabriele Paoloni]

QWRkaW5nIHRvIHRoZSByZWNpcGllbnRzIGxpc3QgdGhlIGF1dGhvcnMgb2YgdGhlIGRyaXZlcnMg
dGhhdCBkZXBlbmQgb24gU3lub3BzeXMgRGVzaWdud2FyZSBhbmQgdGhhdCBhcmUgbm90IGluY2x1
ZGVkDQoNClJlc3BlY3RpdmVseToNCnBjaS1kcmE3eHggS2lzaG9uIFZpamF5IEFicmFoYW0gSSA8
a2lzaG9uQHRpLmNvbT4NCnBjaS1pbXg2IFNlYW4gQ3Jvc3MgPHhvYnNAa29zYWdpLmNvbT4NCnBj
aS1rZXlzdG9uZSBNdXJhbGkgS2FyaWNoZXJpIDxtLWthcmljaGVyaTJAdGkuY29tPg0KcGNpLWxh
eWVyc2NhcGUgTWluZ2h1YW4gTGlhbiA8TWluZ2h1YW4uTGlhbkBmcmVlc2NhbGUuY29tPg0KDQpE
cml2ZXIgQXV0aG9ycyBhbHJlYWR5IGluY2x1ZGVkOg0KcGNpLWV4eW5vcyBKaW5nb28gSGFuIDxq
ZzEuaGFuQHNhbXN1bmcuY29tPg0KcGNpZS1zcGVhcjEzeHggUHJhdHl1c2ggQW5hbmQgPHByYXR5
dXNoLmFuYW5kQHN0LmNvbT4NCg0KQ2hlZXJzDQoNCkdhYg0KDQo+IC0tLS0tT3JpZ2luYWwgTWVz
c2FnZS0tLS0tDQo+IEZyb206IFdhbmd6aG91IChCKQ0KPiBTZW50OiBXZWRuZXNkYXksIEp1bHkg
MDEsIDIwMTUgMTA6NDQgQU0NCj4gVG86IEJqb3JuIEhlbGdhYXM7IEppbmdvbyBIYW47IFByYXR5
dXNoIEFuYW5kOyBBcm5kIEJlcmdtYW5uOyBHYWJyaWVsZQ0KPiBQYW9sb25pOyBKYW1lcyBNb3Jz
ZTsgTGl2aXUgRHVkYXUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWFy
bS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZzsNCj4gZGV2aWNldHJlZUB2Z2VyLmtlcm5lbC5v
cmc7IFl1YW56aGljaGFuZzsgWmh1ZGFjYWk7IHpoYW5nanVrdW87DQo+IHFpdXpoZW5mYTsgTGln
dW96aHUgKEtlbm5ldGgpOyBXYW5nemhvdSAoQikNCj4gU3ViamVjdDogW1BBVENIIHYzIDIvNV0g
UENJOiBkZXNpZ253YXJlOiBBZGQgQVJNNjQgc3VwcG9ydA0KPiANCj4gVGhpcyBwYXRjaCB0cmll
cyB0byB1bmlmeSBBUk0zMiBhbmQgQVJNNjQgUENJZSBpbiBkZXNpZ253YXJlIGRyaXZlci4NCj4g
RGVsZXRlDQo+IGZ1bmN0aW9uIGR3X3BjaWVfc2V0dXAsIGR3X3BjaWVfc2Nhbl9idXMsIGR3X3Bj
aWVfbWFwX2lycSBhbmQgc3RydWN0DQo+IGh3X3BjaSwNCj4gbW92ZSByZWxhdGVkIG9wZXJhdGlv
bnMgdG8gZHdfcGNpZV9ob3N0X2luaXQuIEFsc28gc2V0IHBwLT5yb290X2J1c19ucg0KPiA9IDAg
aW4NCj4gZWFjaCBQQ0llIGhvc3QgZHJpdmVyIHdoaWNoIGlzIGJhc2VkIG9uIHBjaWUtZGVzaWdu
d2FyZS4gVGhpcyBwYXRjaA0KPiBhbHNvIHRyeQ0KPiB0byB1c2Ugb2ZfcGNpX2dldF9ob3N0X2Jy
aWRnZV9yZXNvdXJjZXMgZm9yIEFSTTMyIGFuZCBBUk02NCBhY2NvcmRpbmcNCj4gdG8gdGhlDQo+
IHN1Z2dlc3Rpb24gZm9yIEdhYnJpZWxlWzFdDQo+IA0KPiBJIHRlc3RlZCB0aGlzIHBhdGNoIG9u
IEQwMiBib2FyZCBvZiBIaXNpbGljb24uIEl0IHdvcmtzIHdlbGwuDQo+IEkgaGF2ZSBjb21waWxl
ZCB0aGUgZHJpdmVyIHdpdGggbXVsdGlfdjdfZGVmY29uZmlnLiBIb3dldmVyLCBJIGRvbid0DQo+
IGhhdmUNCj4gQVJNMzIgUENJZSByZWxhdGVkIGJvYXJkIHRvIGRvIHRlc3QuIEl0IHdpbGwgYmUg
YXBwcmVjaWF0ZWQgaWYgc29tZW9uZQ0KPiBjb3VsZA0KPiBoZWxwIHRvIHRlc3QgaXQuDQo+IA0K
PiBTaWduZWQtb2ZmLWJ5OiBaaG91IFdhbmcgPHdhbmd6aG91MUBoaXNpbGljb24uY29tPg0KPiBT
aWduZWQtb2ZmLWJ5OiBBcm5kIEJlcmdtYW5uIDxhcm5kQGFybmRiLmRlPg0KPiBTaWduZWQtb2Zm
LWJ5OiBHYWJyaWVsZSBQYW9sb25pIDxnYWJyaWVsZS5wYW9sb25pQGh1YXdlaS5jb20+DQo+IFRl
c3RlZC1ieTogRmFicmljZSBHYXNuaWVyIDxmYWJyaWNlLmdhc25pZXJAc3QuY29tPg0KPiBUZXN0
ZWQtYnk6IEphbWVzIE1vcnNlIDxqYW1lcy5tb3JzZUBhcm0uY29tPg0KPiANCj4gWzFdIGh0dHA6
Ly93d3cuc3Bpbmljcy5uZXQvbGlzdHMvbGludXgtcGNpL21zZzQyMTk0Lmh0bWwNCj4gLS0tDQo+
ICBkcml2ZXJzL3BjaS9ob3N0L3BjaS1kcmE3eHguYyAgICAgIHwgICAxICsNCj4gIGRyaXZlcnMv
cGNpL2hvc3QvcGNpLWV4eW5vcy5jICAgICAgfCAgIDIgKy0NCj4gIGRyaXZlcnMvcGNpL2hvc3Qv
cGNpLWlteDYuYyAgICAgICAgfCAgIDIgKy0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpLWtleXN0
b25lLWR3LmMgfCAgIDIgKy0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpLWtleXN0b25lLmMgICAg
fCAgIDIgKy0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpLWxheWVyc2NhcGUuYyAgfCAgIDIgKy0N
Cj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMgfCAyNDIgKysrKysrKysrKysr
KysrLS0tLS0tLS0tLS0tLS0NCj4gLS0tLS0tLS0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpZS1k
ZXNpZ253YXJlLmggfCAgMTAgKy0NCj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpZS1zcGVhcjEzeHgu
YyAgfCAgIDIgKy0NCj4gIDkgZmlsZXMgY2hhbmdlZCwgMTEwIGluc2VydGlvbnMoKyksIDE1NSBk
ZWxldGlvbnMoLSkNCj4gDQo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaS1kcmE3
eHguYyBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpLQ0KPiBkcmE3eHguYw0KPiBpbmRleCAyZDU3ZTE5
Li41YzhiNmFiIDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaS1kcmE3eHguYw0K
PiArKysgYi9kcml2ZXJzL3BjaS9ob3N0L3BjaS1kcmE3eHguYw0KPiBAQCAtMjgwLDYgKzI4MCw3
IEBAIHN0YXRpYyBpbnQgX19pbml0IGRyYTd4eF9hZGRfcGNpZV9wb3J0KHN0cnVjdA0KPiBkcmE3
eHhfcGNpZSAqZHJhN3h4LA0KPiANCj4gIAlwcCA9ICZkcmE3eHgtPnBwOw0KPiAgCXBwLT5kZXYg
PSBkZXY7DQo+ICsJcHAtPnJvb3RfYnVzX25yID0gMDsNCj4gIAlwcC0+b3BzID0gJmRyYTd4eF9w
Y2llX2hvc3Rfb3BzOw0KPiANCj4gIAlwcC0+aXJxID0gcGxhdGZvcm1fZ2V0X2lycShwZGV2LCAx
KTsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWV4eW5vcy5jIGIvZHJpdmVy
cy9wY2kvaG9zdC9wY2ktDQo+IGV4eW5vcy5jDQo+IGluZGV4IGMxMzkyMzcuLjRiNmRiNmMgMTAw
NjQ0DQo+IC0tLSBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWV4eW5vcy5jDQo+ICsrKyBiL2RyaXZl
cnMvcGNpL2hvc3QvcGNpLWV4eW5vcy5jDQo+IEBAIC01MzQsNyArNTM0LDcgQEAgc3RhdGljIGlu
dCBfX2luaXQgZXh5bm9zX2FkZF9wY2llX3BvcnQoc3RydWN0DQo+IHBjaWVfcG9ydCAqcHAsDQo+
ICAJCX0NCj4gIAl9DQo+IA0KPiAtCXBwLT5yb290X2J1c19uciA9IC0xOw0KPiArCXBwLT5yb290
X2J1c19uciA9IDA7DQo+ICAJcHAtPm9wcyA9ICZleHlub3NfcGNpZV9ob3N0X29wczsNCj4gDQo+
ICAJcmV0ID0gZHdfcGNpZV9ob3N0X2luaXQocHApOw0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9w
Y2kvaG9zdC9wY2ktaW14Ni5jIGIvZHJpdmVycy9wY2kvaG9zdC9wY2ktaW14Ni5jDQo+IGluZGV4
IGZkYjk1MzYuLmM0YTgwYzUgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWlt
eDYuYw0KPiArKysgYi9kcml2ZXJzL3BjaS9ob3N0L3BjaS1pbXg2LmMNCj4gQEAgLTU0MSw3ICs1
NDEsNyBAQCBzdGF0aWMgaW50IF9faW5pdCBpbXg2X2FkZF9wY2llX3BvcnQoc3RydWN0DQo+IHBj
aWVfcG9ydCAqcHAsDQo+ICAJCX0NCj4gIAl9DQo+IA0KPiAtCXBwLT5yb290X2J1c19uciA9IC0x
Ow0KPiArCXBwLT5yb290X2J1c19uciA9IDA7DQo+ICAJcHAtPm9wcyA9ICZpbXg2X3BjaWVfaG9z
dF9vcHM7DQo+IA0KPiAgCXJldCA9IGR3X3BjaWVfaG9zdF9pbml0KHBwKTsNCj4gZGlmZiAtLWdp
dCBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWtleXN0b25lLWR3LmMgYi9kcml2ZXJzL3BjaS9ob3N0
L3BjaS0NCj4ga2V5c3RvbmUtZHcuYw0KPiBpbmRleCBmMzQ4OTJlLi5iMWU0MTM1IDEwMDY0NA0K
PiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaS1rZXlzdG9uZS1kdy5jDQo+ICsrKyBiL2RyaXZl
cnMvcGNpL2hvc3QvcGNpLWtleXN0b25lLWR3LmMNCj4gQEAgLTMyNyw3ICszMjcsNyBAQCBzdGF0
aWMgdm9pZCBrc19kd19wY2llX2NsZWFyX2RiaV9tb2RlKHZvaWQgX19pb21lbQ0KPiAqcmVnX3Zp
cnQpDQo+ICB2b2lkIGtzX2R3X3BjaWVfc2V0dXBfcmNfYXBwX3JlZ3Moc3RydWN0IGtleXN0b25l
X3BjaWUgKmtzX3BjaWUpDQo+ICB7DQo+ICAJc3RydWN0IHBjaWVfcG9ydCAqcHAgPSAma3NfcGNp
ZS0+cHA7DQo+IC0JdTMyIHN0YXJ0ID0gcHAtPm1lbS5zdGFydCwgZW5kID0gcHAtPm1lbS5lbmQ7
DQo+ICsJdTMyIHN0YXJ0ID0gcHAtPm1lbS0+c3RhcnQsIGVuZCA9IHBwLT5tZW0tPmVuZDsNCj4g
IAlpbnQgaSwgdHJfc2l6ZTsNCj4gDQo+ICAJLyogRGlzYWJsZSBCQVJzIGZvciBpbmJvdW5kIGFj
Y2VzcyAqLw0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvaG9zdC9wY2kta2V5c3RvbmUuYyBi
L2RyaXZlcnMvcGNpL2hvc3QvcGNpLQ0KPiBrZXlzdG9uZS5jDQo+IGluZGV4IDc1MzMzYjAuLmRm
OTFmNWUgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWtleXN0b25lLmMNCj4g
KysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2kta2V5c3RvbmUuYw0KPiBAQCAtMzEyLDcgKzMxMiw3
IEBAIHN0YXRpYyBpbnQgX19pbml0IGtzX2FkZF9wY2llX3BvcnQoc3RydWN0DQo+IGtleXN0b25l
X3BjaWUgKmtzX3BjaWUsDQo+ICAJCQlyZXR1cm4gcmV0Ow0KPiAgCX0NCj4gDQo+IC0JcHAtPnJv
b3RfYnVzX25yID0gLTE7DQo+ICsJcHAtPnJvb3RfYnVzX25yID0gMDsNCj4gIAlwcC0+b3BzID0g
JmtleXN0b25lX3BjaWVfaG9zdF9vcHM7DQo+ICAJcmV0ID0ga3NfZHdfcGNpZV9ob3N0X2luaXQo
a3NfcGNpZSwga3NfcGNpZS0+bXNpX2ludGNfbnApOw0KPiAgCWlmIChyZXQpIHsNCj4gZGlmZiAt
LWdpdCBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWxheWVyc2NhcGUuYyBiL2RyaXZlcnMvcGNpL2hv
c3QvcGNpLQ0KPiBsYXllcnNjYXBlLmMNCj4gaW5kZXggNGE2ZTYyZi4uNWM3YTljNCAxMDA2NDQN
Cj4gLS0tIGEvZHJpdmVycy9wY2kvaG9zdC9wY2ktbGF5ZXJzY2FwZS5jDQo+ICsrKyBiL2RyaXZl
cnMvcGNpL2hvc3QvcGNpLWxheWVyc2NhcGUuYw0KPiBAQCAtMTAxLDcgKzEwMSw3IEBAIHN0YXRp
YyBpbnQgbHNfYWRkX3BjaWVfcG9ydChzdHJ1Y3QgbHNfcGNpZSAqcGNpZSkNCj4gIAlwcCA9ICZw
Y2llLT5wcDsNCj4gIAlwcC0+ZGV2ID0gcGNpZS0+ZGV2Ow0KPiAgCXBwLT5kYmlfYmFzZSA9IHBj
aWUtPmRiaTsNCj4gLQlwcC0+cm9vdF9idXNfbnIgPSAtMTsNCj4gKwlwcC0+cm9vdF9idXNfbnIg
PSAwOw0KPiAgCXBwLT5vcHMgPSAmbHNfcGNpZV9ob3N0X29wczsNCj4gDQo+ICAJcmV0ID0gZHdf
cGNpZV9ob3N0X2luaXQocHApOw0KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvaG9zdC9wY2ll
LWRlc2lnbndhcmUuYw0KPiBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMNCj4g
aW5kZXggMmU5Zjg0Zi4uODQ0ZmViZWUgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvcGNpL2hvc3Qv
cGNpZS1kZXNpZ253YXJlLmMNCj4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndh
cmUuYw0KPiBAQCAtMTEsNiArMTEsNyBAQA0KPiAgICogcHVibGlzaGVkIGJ5IHRoZSBGcmVlIFNv
ZnR3YXJlIEZvdW5kYXRpb24uDQo+ICAgKi8NCj4gDQo+ICsjaW5jbHVkZSA8bGludXgvaGFyZGly
cS5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L2lycS5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L2lycWRv
bWFpbi5oPg0KPiAgI2luY2x1ZGUgPGxpbnV4L2tlcm5lbC5oPg0KPiBAQCAtNjcsMTYgKzY4LDcg
QEANCj4gICNkZWZpbmUgUENJRV9BVFVfRlVOQyh4KQkJKCgoeCkgJiAweDcpIDw8IDE2KQ0KPiAg
I2RlZmluZSBQQ0lFX0FUVV9VUFBFUl9UQVJHRVQJCTB4OTFDDQo+IA0KPiAtc3RhdGljIHN0cnVj
dCBod19wY2kgZHdfcGNpOw0KPiAtDQo+IC1zdGF0aWMgdW5zaWduZWQgbG9uZyBnbG9iYWxfaW9f
b2Zmc2V0Ow0KPiAtDQo+IC1zdGF0aWMgaW5saW5lIHN0cnVjdCBwY2llX3BvcnQgKnN5c190b19w
Y2llKHN0cnVjdCBwY2lfc3lzX2RhdGEgKnN5cykNCj4gLXsNCj4gLQlCVUdfT04oIXN5cy0+cHJp
dmF0ZV9kYXRhKTsNCj4gLQ0KPiAtCXJldHVybiBzeXMtPnByaXZhdGVfZGF0YTsNCj4gLX0NCj4g
K3N0YXRpYyBzdHJ1Y3QgcGNpX29wcyBkd19wY2llX29wczsNCj4gDQo+ICBpbnQgZHdfcGNpZV9j
ZmdfcmVhZCh2b2lkIF9faW9tZW0gKmFkZHIsIGludCB3aGVyZSwgaW50IHNpemUsIHUzMiAqdmFs
KQ0KPiAgew0KPiBAQCAtMjM4LDcgKzIzMCw3IEBAIHN0YXRpYyB2b2lkIGR3X3BjaWVfbXNpX3Nl
dF9pcnEoc3RydWN0IHBjaWVfcG9ydA0KPiAqcHAsIGludCBpcnEpDQo+ICBzdGF0aWMgaW50IGFz
c2lnbl9pcnEoaW50IG5vX2lycXMsIHN0cnVjdCBtc2lfZGVzYyAqZGVzYywgaW50ICpwb3MpDQo+
ICB7DQo+ICAJaW50IGlycSwgcG9zMCwgaTsNCj4gLQlzdHJ1Y3QgcGNpZV9wb3J0ICpwcCA9IHN5
c190b19wY2llKGRlc2MtPmRldi0+YnVzLT5zeXNkYXRhKTsNCj4gKwlzdHJ1Y3QgcGNpZV9wb3J0
ICpwcCA9IGRlc2MtPmRldi0+YnVzLT5zeXNkYXRhOw0KPiANCj4gIAlwb3MwID0gYml0bWFwX2Zp
bmRfZnJlZV9yZWdpb24ocHAtPm1zaV9pcnFfaW5fdXNlLCBNQVhfTVNJX0lSUVMsDQo+ICAJCQkJ
ICAgICAgIG9yZGVyX2Jhc2VfMihub19pcnFzKSk7DQo+IEBAIC0yODEsNyArMjczLDcgQEAgc3Rh
dGljIGludCBkd19tc2lfc2V0dXBfaXJxKHN0cnVjdCBtc2lfY29udHJvbGxlcg0KPiAqY2hpcCwg
c3RydWN0IHBjaV9kZXYgKnBkZXYsDQo+ICB7DQo+ICAJaW50IGlycSwgcG9zOw0KPiAgCXN0cnVj
dCBtc2lfbXNnIG1zZzsNCj4gLQlzdHJ1Y3QgcGNpZV9wb3J0ICpwcCA9IHN5c190b19wY2llKHBk
ZXYtPmJ1cy0+c3lzZGF0YSk7DQo+ICsJc3RydWN0IHBjaWVfcG9ydCAqcHAgPSBwZGV2LT5idXMt
PnN5c2RhdGE7DQo+IA0KPiAgCWlmIChkZXNjLT5tc2lfYXR0cmliLmlzX21zaXgpDQo+ICAJCXJl
dHVybiAtRUlOVkFMOw0KPiBAQCAtMzEwLDcgKzMwMiw3IEBAIHN0YXRpYyB2b2lkIGR3X21zaV90
ZWFyZG93bl9pcnEoc3RydWN0DQo+IG1zaV9jb250cm9sbGVyICpjaGlwLCB1bnNpZ25lZCBpbnQg
aXJxKQ0KPiAgew0KPiAgCXN0cnVjdCBpcnFfZGF0YSAqZGF0YSA9IGlycV9nZXRfaXJxX2RhdGEo
aXJxKTsNCj4gIAlzdHJ1Y3QgbXNpX2Rlc2MgKm1zaSA9IGlycV9kYXRhX2dldF9tc2koZGF0YSk7
DQo+IC0Jc3RydWN0IHBjaWVfcG9ydCAqcHAgPSBzeXNfdG9fcGNpZShtc2ktPmRldi0+YnVzLT5z
eXNkYXRhKTsNCj4gKwlzdHJ1Y3QgcGNpZV9wb3J0ICpwcCA9IG1zaS0+ZGV2LT5idXMtPnN5c2Rh
dGE7DQo+IA0KPiAgCWNsZWFyX2lycV9yYW5nZShwcCwgaXJxLCAxLCBkYXRhLT5od2lycSk7DQo+
ICB9DQo+IEBAIC0zNDIsMTYgKzMzNCwyNCBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGlycV9kb21h
aW5fb3BzIG1zaV9kb21haW5fb3BzDQo+ID0gew0KPiAgCS5tYXAgPSBkd19wY2llX21zaV9tYXAs
DQo+ICB9Ow0KPiANCj4gLWludCBkd19wY2llX2hvc3RfaW5pdChzdHJ1Y3QgcGNpZV9wb3J0ICpw
cCkNCj4gK2ludCBfX2luaXQgZHdfcGNpZV9ob3N0X2luaXQoc3RydWN0IHBjaWVfcG9ydCAqcHAp
DQo+ICB7DQo+ICAJc3RydWN0IGRldmljZV9ub2RlICpucCA9IHBwLT5kZXYtPm9mX25vZGU7DQo+
ICAJc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldiA9IHRvX3BsYXRmb3JtX2RldmljZShwcC0+
ZGV2KTsNCj4gLQlzdHJ1Y3Qgb2ZfcGNpX3JhbmdlIHJhbmdlOw0KPiAtCXN0cnVjdCBvZl9wY2lf
cmFuZ2VfcGFyc2VyIHBhcnNlcjsNCj4gKwlzdHJ1Y3QgcGNpX2J1cyAqYnVzOw0KPiAgCXN0cnVj
dCByZXNvdXJjZSAqY2ZnX3JlczsNCj4gKwlMSVNUX0hFQUQocmVzKTsNCj4gIAl1MzIgdmFsLCBu
YSwgbnM7DQo+ICAJY29uc3QgX19iZTMyICphZGRycDsNCj4gIAlpbnQgaSwgaW5kZXgsIHJldDsN
Cj4gKwlpbnQgcmxlbjsNCj4gKwlzdHJ1Y3QgcmVzb3VyY2VfZW50cnkgKndpbjsNCj4gKwljb25z
dCBfX2JlMzIgKnBhcnNlcl9yYW5nZV9lbmQgPSBvZl9nZXRfcHJvcGVydHkobnAsICJyYW5nZXMi
LA0KPiAmcmxlbik7DQo+ICsNCj4gKwlpZiAocGFyc2VyX3JhbmdlX2VuZCA9PSBOVUxMKQ0KPiAr
CQkJcmV0dXJuIC1FTk9FTlQ7DQo+ICsJcGFyc2VyX3JhbmdlX2VuZCArPSBybGVuL3NpemVvZihf
X2JlMzIpOw0KPiArDQo+IA0KPiAgCS8qIEZpbmQgdGhlIGFkZHJlc3MgY2VsbCBzaXplIGFuZCB0
aGUgbnVtYmVyIG9mIGNlbGxzIGluIG9yZGVyIHRvDQo+IGdldA0KPiAgCSAqIHRoZSB1bnRyYW5z
bGF0ZWQgYWRkcmVzcy4NCj4gQEAgLTM3NSw3OCArMzc1LDY3IEBAIGludCBkd19wY2llX2hvc3Rf
aW5pdChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCkNCj4gIAkJZGV2X2VycihwcC0+ZGV2LCAibWlzc2lu
ZyAqY29uZmlnKiByZWcgc3BhY2VcbiIpOw0KPiAgCX0NCj4gDQo+IC0JaWYgKG9mX3BjaV9yYW5n
ZV9wYXJzZXJfaW5pdCgmcGFyc2VyLCBucCkpIHsNCj4gLQkJZGV2X2VycihwcC0+ZGV2LCAibWlz
c2luZyByYW5nZXMgcHJvcGVydHlcbiIpOw0KPiAtCQlyZXR1cm4gLUVJTlZBTDsNCj4gLQl9DQo+
ICsJcmV0ID0gb2ZfcGNpX2dldF9ob3N0X2JyaWRnZV9yZXNvdXJjZXMobnAsIDAsIDB4ZmYsICZy
ZXMsICZwcC0NCj4gPmlvX2Jhc2UpOw0KPiArCWlmIChyZXQpDQo+ICsJCXJldHVybiByZXQ7DQo+
IA0KPiAgCS8qIEdldCB0aGUgSS9PIGFuZCBtZW1vcnkgcmFuZ2VzIGZyb20gRFQgKi8NCj4gLQlm
b3JfZWFjaF9vZl9wY2lfcmFuZ2UoJnBhcnNlciwgJnJhbmdlKSB7DQo+IC0JCXVuc2lnbmVkIGxv
bmcgcmVzdHlwZSA9IHJhbmdlLmZsYWdzICYgSU9SRVNPVVJDRV9UWVBFX0JJVFM7DQo+IC0NCj4g
LQkJaWYgKHJlc3R5cGUgPT0gSU9SRVNPVVJDRV9JTykgew0KPiAtCQkJb2ZfcGNpX3JhbmdlX3Rv
X3Jlc291cmNlKCZyYW5nZSwgbnAsICZwcC0+aW8pOw0KPiAtCQkJcHAtPmlvLm5hbWUgPSAiSS9P
IjsNCj4gLQkJCXBwLT5pby5zdGFydCA9IG1heF90KHJlc291cmNlX3NpemVfdCwNCj4gLQkJCQkJ
ICAgICBQQ0lCSU9TX01JTl9JTywNCj4gLQkJCQkJICAgICByYW5nZS5wY2lfYWRkciArIGdsb2Jh
bF9pb19vZmZzZXQpOw0KPiAtCQkJcHAtPmlvLmVuZCA9IG1pbl90KHJlc291cmNlX3NpemVfdCwN
Cj4gLQkJCQkJICAgSU9fU1BBQ0VfTElNSVQsDQo+IC0JCQkJCSAgIHJhbmdlLnBjaV9hZGRyICsg
cmFuZ2Uuc2l6ZQ0KPiAtCQkJCQkgICArIGdsb2JhbF9pb19vZmZzZXQgLSAxKTsNCj4gLQkJCXBw
LT5pb19zaXplID0gcmVzb3VyY2Vfc2l6ZSgmcHAtPmlvKTsNCj4gLQkJCXBwLT5pb19idXNfYWRk
ciA9IHJhbmdlLnBjaV9hZGRyOw0KPiAtCQkJcHAtPmlvX2Jhc2UgPSByYW5nZS5jcHVfYWRkcjsN
Cj4gLQ0KPiAtCQkJLyogRmluZCB0aGUgdW50cmFuc2xhdGVkIElPIHNwYWNlIGFkZHJlc3MgKi8N
Cj4gLQkJCXBwLT5pb19tb2RfYmFzZSA9IG9mX3JlYWRfbnVtYmVyKHBhcnNlci5yYW5nZSAtDQo+
IC0JCQkJCQkJIHBhcnNlci5ucCArIG5hLCBucyk7DQo+IC0JCX0NCj4gLQkJaWYgKHJlc3R5cGUg
PT0gSU9SRVNPVVJDRV9NRU0pIHsNCj4gLQkJCW9mX3BjaV9yYW5nZV90b19yZXNvdXJjZSgmcmFu
Z2UsIG5wLCAmcHAtPm1lbSk7DQo+IC0JCQlwcC0+bWVtLm5hbWUgPSAiTUVNIjsNCj4gLQkJCXBw
LT5tZW1fc2l6ZSA9IHJlc291cmNlX3NpemUoJnBwLT5tZW0pOw0KPiAtCQkJcHAtPm1lbV9idXNf
YWRkciA9IHJhbmdlLnBjaV9hZGRyOw0KPiAtDQo+IC0JCQkvKiBGaW5kIHRoZSB1bnRyYW5zbGF0
ZWQgTUVNIHNwYWNlIGFkZHJlc3MgKi8NCj4gLQkJCXBwLT5tZW1fbW9kX2Jhc2UgPSBvZl9yZWFk
X251bWJlcihwYXJzZXIucmFuZ2UgLQ0KPiAtCQkJCQkJCSAgcGFyc2VyLm5wICsgbmEsIG5zKTsN
Cj4gLQkJfQ0KPiAtCQlpZiAocmVzdHlwZSA9PSAwKSB7DQo+IC0JCQlvZl9wY2lfcmFuZ2VfdG9f
cmVzb3VyY2UoJnJhbmdlLCBucCwgJnBwLT5jZmcpOw0KPiAtCQkJcHAtPmNmZzBfc2l6ZSA9IHJl
c291cmNlX3NpemUoJnBwLT5jZmcpLzI7DQo+IC0JCQlwcC0+Y2ZnMV9zaXplID0gcmVzb3VyY2Vf
c2l6ZSgmcHAtPmNmZykvMjsNCj4gLQkJCXBwLT5jZmcwX2Jhc2UgPSBwcC0+Y2ZnLnN0YXJ0Ow0K
PiAtCQkJcHAtPmNmZzFfYmFzZSA9IHBwLT5jZmcuc3RhcnQgKyBwcC0+Y2ZnMF9zaXplOw0KPiAr
CXJlc291cmNlX2xpc3RfZm9yX2VhY2hfZW50cnkod2luLCAmcmVzKSB7DQo+ICsJCXN3aXRjaCAo
cmVzb3VyY2VfdHlwZSh3aW4tPnJlcykpIHsNCj4gKwkJY2FzZSBJT1JFU09VUkNFX0lPOg0KPiAr
CQkJcHAtPmlvID0gd2luLT5yZXM7DQo+ICsJCQlwcC0+aW8tPm5hbWUgPSAiSS9PIjsNCj4gKwkJ
CXBwLT5pb19zaXplID0gcmVzb3VyY2Vfc2l6ZShwcC0+aW8pOw0KPiArCQkJcHAtPmlvX2J1c19h
ZGRyID0gcHAtPmlvLT5zdGFydCAtIHdpbi0+b2Zmc2V0Ow0KPiArCQkJLyogbWFnaWMgNSBiZWxv
dyBjb21lcyBmcm9tIG1hZ2ljIG5hIGFuZCBucyBpbg0KPiArCQkJICogb2ZfcGNpX3JhbmdlX3Bh
cnNlcl9pbml0KCkgICAgICAgICAgICAgICAgICovDQo+ICsJCQlwcC0+aW9fbW9kX2Jhc2UgPSBv
Zl9yZWFkX251bWJlcihwYXJzZXJfcmFuZ2VfZW5kIC0NCj4gKwkJCQkJb2Zfbl9hZGRyX2NlbGxz
KG5wKSAtIDUgKyBuYSwgbnMpOw0KPiArCQkJcmV0ID0gcGNpX3JlbWFwX2lvc3BhY2UocHAtPmlv
LCBwcC0+aW9fYmFzZSk7DQo+ICsJCQlpZiAocmV0KSB7DQo+ICsJCQkJZGV2X3dhcm4ocHAtPmRl
diwgImVycm9yICVkOiBmYWlsZWQgdG8gbWFwDQo+IHJlc291cmNlICVwUlxuIiwNCj4gKwkJCQly
ZXQsIHBwLT5pbyk7DQo+ICsJCQljb250aW51ZTsNCj4gKwkJCX0NCj4gKwkJCWJyZWFrOw0KPiAr
CQljYXNlIElPUkVTT1VSQ0VfTUVNOg0KPiArCQkJcHAtPm1lbSA9IHdpbi0+cmVzOw0KPiArCQkJ
cHAtPm1lbS0+bmFtZSA9ICJNRU0iOw0KPiArCQkJcHAtPm1lbV9zaXplID0gcmVzb3VyY2Vfc2l6
ZShwcC0+bWVtKTsNCj4gKwkJCXBwLT5tZW1fYnVzX2FkZHIgPSBwcC0+bWVtLT5zdGFydCAtIHdp
bi0+b2Zmc2V0Ow0KPiArCQkJcHAtPm1lbV9tb2RfYmFzZSA9IG9mX3JlYWRfbnVtYmVyKHBhcnNl
cl9yYW5nZV9lbmQgLQ0KPiArCQkJCQlvZl9uX2FkZHJfY2VsbHMobnApIC0gNSArIG5hLCBucyk7
DQo+ICsJCQlicmVhazsNCj4gKwkJY2FzZSAwOg0KPiArCQkJcHAtPmNmZyA9IHdpbi0+cmVzOw0K
PiArCQkJcHAtPmNmZzBfc2l6ZSA9IHJlc291cmNlX3NpemUocHAtPmNmZykvMjsNCj4gKwkJCXBw
LT5jZmcxX3NpemUgPSByZXNvdXJjZV9zaXplKHBwLT5jZmcpLzI7DQo+ICsJCQlwcC0+Y2ZnMF9i
YXNlID0gcHAtPmNmZy0+c3RhcnQ7DQo+ICsJCQlwcC0+Y2ZnMV9iYXNlID0gcHAtPmNmZy0+c3Rh
cnQgKyBwcC0+Y2ZnMF9zaXplOw0KPiANCj4gIAkJCS8qIEZpbmQgdGhlIHVudHJhbnNsYXRlZCBj
b25maWd1cmF0aW9uIHNwYWNlIGFkZHJlc3MNCj4gKi8NCj4gLQkJCXBwLT5jZmcwX21vZF9iYXNl
ID0gb2ZfcmVhZF9udW1iZXIocGFyc2VyLnJhbmdlIC0NCj4gLQkJCQkJCQkgICBwYXJzZXIubnAg
KyBuYSwgbnMpOw0KPiAtCQkJcHAtPmNmZzFfbW9kX2Jhc2UgPSBwcC0+Y2ZnMF9tb2RfYmFzZSAr
DQo+IC0JCQkJCSAgICBwcC0+Y2ZnMF9zaXplOw0KPiArCQkJcHAtPmNmZzBfbW9kX2Jhc2UgPSBv
Zl9yZWFkX251bWJlcihwYXJzZXJfcmFuZ2VfZW5kIC0NCj4gKwkJCQkJb2Zfbl9hZGRyX2NlbGxz
KG5wKSAtIDUgKyBuYSwgbnMpOw0KPiArCQkJcHAtPmNmZzFfbW9kX2Jhc2UgPSBwcC0+Y2ZnMF9t
b2RfYmFzZSArIHBwLT5jZmcwX3NpemU7DQo+ICsJCQlicmVhazsNCj4gKwkJY2FzZSBJT1JFU09V
UkNFX0JVUzoNCj4gKwkJCXBwLT5idXNuID0gd2luLT5yZXM7DQo+ICsJCQlicmVhazsNCj4gKwkJ
ZGVmYXVsdDoNCj4gKwkJCWNvbnRpbnVlOw0KPiAgCQl9DQo+ICAJfQ0KPiANCj4gLQlyZXQgPSBv
Zl9wY2lfcGFyc2VfYnVzX3JhbmdlKG5wLCAmcHAtPmJ1c24pOw0KPiAtCWlmIChyZXQgPCAwKSB7
DQo+IC0JCXBwLT5idXNuLm5hbWUgPSBucC0+bmFtZTsNCj4gLQkJcHAtPmJ1c24uc3RhcnQgPSAw
Ow0KPiAtCQlwcC0+YnVzbi5lbmQgPSAweGZmOw0KPiAtCQlwcC0+YnVzbi5mbGFncyA9IElPUkVT
T1VSQ0VfQlVTOw0KPiAtCQlkZXZfZGJnKHBwLT5kZXYsICJmYWlsZWQgdG8gcGFyc2UgYnVzLXJh
bmdlIHByb3BlcnR5OiAlZCwNCj4gdXNpbmcgZGVmYXVsdCAlcFJcbiIsDQo+IC0JCQlyZXQsICZw
cC0+YnVzbik7DQo+IC0JfQ0KPiAtDQo+ICAJaWYgKCFwcC0+ZGJpX2Jhc2UpIHsNCj4gLQkJcHAt
PmRiaV9iYXNlID0gZGV2bV9pb3JlbWFwKHBwLT5kZXYsIHBwLT5jZmcuc3RhcnQsDQo+IC0JCQkJ
CXJlc291cmNlX3NpemUoJnBwLT5jZmcpKTsNCj4gKwkJcHAtPmRiaV9iYXNlID0gZGV2bV9pb3Jl
bWFwKHBwLT5kZXYsIHBwLT5jZmctPnN0YXJ0LA0KPiArCQkJCQlyZXNvdXJjZV9zaXplKHBwLT5j
ZmcpKTsNCj4gIAkJaWYgKCFwcC0+ZGJpX2Jhc2UpIHsNCj4gIAkJCWRldl9lcnIocHAtPmRldiwg
ImVycm9yIHdpdGggaW9yZW1hcFxuIik7DQo+ICAJCQlyZXR1cm4gLUVOT01FTTsNCj4gIAkJfQ0K
PiAgCX0NCj4gDQo+IC0JcHAtPm1lbV9iYXNlID0gcHAtPm1lbS5zdGFydDsNCj4gKwlwcC0+bWVt
X2Jhc2UgPSBwcC0+bWVtLT5zdGFydDsNCj4gDQo+ICAJaWYgKCFwcC0+dmFfY2ZnMF9iYXNlKSB7
DQo+ICAJCXBwLT52YV9jZmcwX2Jhc2UgPSBkZXZtX2lvcmVtYXAocHAtPmRldiwgcHAtPmNmZzBf
YmFzZSwNCj4gQEAgLTQ5MywyNCArNDgyLDQ3IEBAIGludCBkd19wY2llX2hvc3RfaW5pdChzdHJ1
Y3QgcGNpZV9wb3J0ICpwcCkNCj4gIAlpZiAocHAtPm9wcy0+aG9zdF9pbml0KQ0KPiAgCQlwcC0+
b3BzLT5ob3N0X2luaXQocHApOw0KPiANCj4gLQlkd19wY2llX3dyX293bl9jb25mKHBwLCBQQ0lf
QkFTRV9BRERSRVNTXzAsIDQsIDApOw0KPiArCWlmIChkd19wY2llX3dyX293bl9jb25mKHBwLCBQ
Q0lfQkFTRV9BRERSRVNTXzAsIDQsIDApDQo+ICsJCQkhPSBQQ0lCSU9TX1NVQ0NFU1NGVUwpDQo+
ICsJCXJldHVybiAtRUlOVkFMOw0KPiANCj4gIAkvKiBwcm9ncmFtIGNvcnJlY3QgY2xhc3MgZm9y
IFJDICovDQo+IC0JZHdfcGNpZV93cl9vd25fY29uZihwcCwgUENJX0NMQVNTX0RFVklDRSwgMiwN
Cj4gUENJX0NMQVNTX0JSSURHRV9QQ0kpOw0KPiArCWlmIChkd19wY2llX3dyX293bl9jb25mKHBw
LCBQQ0lfQ0xBU1NfREVWSUNFLCAyLA0KPiBQQ0lfQ0xBU1NfQlJJREdFX1BDSSkNCj4gKwkJCSE9
IFBDSUJJT1NfU1VDQ0VTU0ZVTCkNCj4gKwkJcmV0dXJuIC1FSU5WQUw7DQo+ICsNCj4gKwlpZiAo
ZHdfcGNpZV9yZF9vd25fY29uZihwcCwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NPTlRST0wsIDQs
DQo+ICZ2YWwpDQo+ICsJCQkhPSBQQ0lCSU9TX1NVQ0NFU1NGVUwpDQo+ICsJCXJldHVybiAtRUlO
VkFMOw0KPiANCj4gLQlkd19wY2llX3JkX293bl9jb25mKHBwLCBQQ0lFX0xJTktfV0lEVEhfU1BF
RURfQ09OVFJPTCwgNCwgJnZhbCk7DQo+ICAJdmFsIHw9IFBPUlRfTE9HSUNfU1BFRURfQ0hBTkdF
Ow0KPiAtCWR3X3BjaWVfd3Jfb3duX2NvbmYocHAsIFBDSUVfTElOS19XSURUSF9TUEVFRF9DT05U
Uk9MLCA0LCB2YWwpOw0KPiANCj4gLSNpZmRlZiBDT05GSUdfUENJX01TSQ0KPiAtCWR3X3BjaWVf
bXNpX2NoaXAuZGV2ID0gcHAtPmRldjsNCj4gLQlkd19wY2kubXNpX2N0cmwgPSAmZHdfcGNpZV9t
c2lfY2hpcDsNCj4gKwlpZiAoZHdfcGNpZV93cl9vd25fY29uZihwcCwgUENJRV9MSU5LX1dJRFRI
X1NQRUVEX0NPTlRST0wsIDQsIHZhbCkNCj4gKwkJCSE9IFBDSUJJT1NfU1VDQ0VTU0ZVTCkNCj4g
KwkJcmV0dXJuIC1FSU5WQUw7DQo+ICsNCj4gKwlidXMgPSBwY2lfY3JlYXRlX3Jvb3RfYnVzKHBw
LT5kZXYsIHBwLT5yb290X2J1c19uciwgJmR3X3BjaWVfb3BzLA0KPiArCQkJICAgICAgcHAsICZy
ZXMpOw0KPiArCWlmICghYnVzKQ0KPiArCQlyZXR1cm4gLUVOT01FTTsNCj4gKw0KPiArI2lmZGVm
IENPTkZJR19HRU5FUklDX01TSV9JUlFfRE9NQUlODQo+ICsJYnVzLT5tc2kgPSBjb250YWluZXJf
b2YoJnBwLT5pcnFfZG9tYWluLCBzdHJ1Y3QgbXNpX2NvbnRyb2xsZXIsDQo+IGRvbWFpbik7DQo+
ICsjZWxzZQ0KPiArCWJ1cy0+bXNpID0gJmR3X3BjaWVfbXNpX2NoaXA7DQo+ICAjZW5kaWYNCj4g
DQo+IC0JZHdfcGNpLm5yX2NvbnRyb2xsZXJzID0gMTsNCj4gLQlkd19wY2kucHJpdmF0ZV9kYXRh
ID0gKHZvaWQgKiopJnBwOw0KPiArCXBjaV9zY2FuX2NoaWxkX2J1cyhidXMpOw0KPiArCWlmIChw
cC0+b3BzLT5zY2FuX2J1cykNCj4gKwkJcHAtPm9wcy0+c2Nhbl9idXMocHApOw0KPiANCj4gLQlw
Y2lfY29tbW9uX2luaXRfZGV2KHBwLT5kZXYsICZkd19wY2kpOw0KPiArI2lmZGVmIENPTkZJR19B
Uk0NCj4gKwkvKiBzdXBwb3J0IG9sZCBkdGJzIHRoYXQgaW5jb3JyZWN0bHkgZGVzY3JpYmUgSVJR
cyAqLw0KPiArCXBjaV9maXh1cF9pcnFzKHBjaV9jb21tb25fc3dpenpsZSwgb2ZfaXJxX3BhcnNl
X2FuZF9tYXBfcGNpKTsNCj4gKyNlbmRpZg0KPiArDQo+ICsJcGNpX2Fzc2lnbl91bmFzc2lnbmVk
X2J1c19yZXNvdXJjZXMoYnVzKTsNCj4gKwlwY2lfYnVzX2FkZF9kZXZpY2VzKGJ1cyk7DQo+IA0K
PiAgCXJldHVybiAwOw0KPiAgfQ0KPiBAQCAtNjUzLDcgKzY2NSw3IEBAIHN0YXRpYyBpbnQgZHdf
cGNpZV92YWxpZF9jb25maWcoc3RydWN0IHBjaWVfcG9ydA0KPiAqcHAsDQo+ICBzdGF0aWMgaW50
IGR3X3BjaWVfcmRfY29uZihzdHJ1Y3QgcGNpX2J1cyAqYnVzLCB1MzIgZGV2Zm4sIGludCB3aGVy
ZSwNCj4gIAkJCWludCBzaXplLCB1MzIgKnZhbCkNCj4gIHsNCj4gLQlzdHJ1Y3QgcGNpZV9wb3J0
ICpwcCA9IHN5c190b19wY2llKGJ1cy0+c3lzZGF0YSk7DQo+ICsJc3RydWN0IHBjaWVfcG9ydCAq
cHAgPSBidXMtPnN5c2RhdGE7DQo+ICAJaW50IHJldDsNCj4gDQo+ICAJaWYgKGR3X3BjaWVfdmFs
aWRfY29uZmlnKHBwLCBidXMsIFBDSV9TTE9UKGRldmZuKSkgPT0gMCkgew0KPiBAQCAtNjc3LDcg
KzY4OSw3IEBAIHN0YXRpYyBpbnQgZHdfcGNpZV9yZF9jb25mKHN0cnVjdCBwY2lfYnVzICpidXMs
IHUzMg0KPiBkZXZmbiwgaW50IHdoZXJlLA0KPiAgc3RhdGljIGludCBkd19wY2llX3dyX2NvbmYo
c3RydWN0IHBjaV9idXMgKmJ1cywgdTMyIGRldmZuLA0KPiAgCQkJaW50IHdoZXJlLCBpbnQgc2l6
ZSwgdTMyIHZhbCkNCj4gIHsNCj4gLQlzdHJ1Y3QgcGNpZV9wb3J0ICpwcCA9IHN5c190b19wY2ll
KGJ1cy0+c3lzZGF0YSk7DQo+ICsJc3RydWN0IHBjaWVfcG9ydCAqcHAgPSBidXMtPnN5c2RhdGE7
DQo+ICAJaW50IHJldDsNCj4gDQo+ICAJaWYgKGR3X3BjaWVfdmFsaWRfY29uZmlnKHBwLCBidXMs
IFBDSV9TTE9UKGRldmZuKSkgPT0gMCkNCj4gQEAgLTcwMSw2NCArNzEzLDYgQEAgc3RhdGljIHN0
cnVjdCBwY2lfb3BzIGR3X3BjaWVfb3BzID0gew0KPiAgCS53cml0ZSA9IGR3X3BjaWVfd3JfY29u
ZiwNCj4gIH07DQo+IA0KPiAtc3RhdGljIGludCBkd19wY2llX3NldHVwKGludCBuciwgc3RydWN0
IHBjaV9zeXNfZGF0YSAqc3lzKQ0KPiAtew0KPiAtCXN0cnVjdCBwY2llX3BvcnQgKnBwOw0KPiAt
DQo+IC0JcHAgPSBzeXNfdG9fcGNpZShzeXMpOw0KPiAtDQo+IC0JaWYgKGdsb2JhbF9pb19vZmZz
ZXQgPCBTWl8xTSAmJiBwcC0+aW9fc2l6ZSA+IDApIHsNCj4gLQkJc3lzLT5pb19vZmZzZXQgPSBn
bG9iYWxfaW9fb2Zmc2V0IC0gcHAtPmlvX2J1c19hZGRyOw0KPiAtCQlwY2lfaW9yZW1hcF9pbyhn
bG9iYWxfaW9fb2Zmc2V0LCBwcC0+aW9fYmFzZSk7DQo+IC0JCWdsb2JhbF9pb19vZmZzZXQgKz0g
U1pfNjRLOw0KPiAtCQlwY2lfYWRkX3Jlc291cmNlX29mZnNldCgmc3lzLT5yZXNvdXJjZXMsICZw
cC0+aW8sDQo+IC0JCQkJCXN5cy0+aW9fb2Zmc2V0KTsNCj4gLQl9DQo+IC0NCj4gLQlzeXMtPm1l
bV9vZmZzZXQgPSBwcC0+bWVtLnN0YXJ0IC0gcHAtPm1lbV9idXNfYWRkcjsNCj4gLQlwY2lfYWRk
X3Jlc291cmNlX29mZnNldCgmc3lzLT5yZXNvdXJjZXMsICZwcC0+bWVtLCBzeXMtDQo+ID5tZW1f
b2Zmc2V0KTsNCj4gLQlwY2lfYWRkX3Jlc291cmNlKCZzeXMtPnJlc291cmNlcywgJnBwLT5idXNu
KTsNCj4gLQ0KPiAtCXJldHVybiAxOw0KPiAtfQ0KPiAtDQo+IC1zdGF0aWMgc3RydWN0IHBjaV9i
dXMgKmR3X3BjaWVfc2Nhbl9idXMoaW50IG5yLCBzdHJ1Y3QgcGNpX3N5c19kYXRhDQo+ICpzeXMp
DQo+IC17DQo+IC0Jc3RydWN0IHBjaV9idXMgKmJ1czsNCj4gLQlzdHJ1Y3QgcGNpZV9wb3J0ICpw
cCA9IHN5c190b19wY2llKHN5cyk7DQo+IC0NCj4gLQlwcC0+cm9vdF9idXNfbnIgPSBzeXMtPmJ1
c25yOw0KPiAtCWJ1cyA9IHBjaV9jcmVhdGVfcm9vdF9idXMocHAtPmRldiwgc3lzLT5idXNuciwN
Cj4gLQkJCQkgICZkd19wY2llX29wcywgc3lzLCAmc3lzLT5yZXNvdXJjZXMpOw0KPiAtCWlmICgh
YnVzKQ0KPiAtCQlyZXR1cm4gTlVMTDsNCj4gLQ0KPiAtCXBjaV9zY2FuX2NoaWxkX2J1cyhidXMp
Ow0KPiAtDQo+IC0JaWYgKGJ1cyAmJiBwcC0+b3BzLT5zY2FuX2J1cykNCj4gLQkJcHAtPm9wcy0+
c2Nhbl9idXMocHApOw0KPiAtDQo+IC0JcmV0dXJuIGJ1czsNCj4gLX0NCj4gLQ0KPiAtc3RhdGlj
IGludCBkd19wY2llX21hcF9pcnEoY29uc3Qgc3RydWN0IHBjaV9kZXYgKmRldiwgdTggc2xvdCwg
dTggcGluKQ0KPiAtew0KPiAtCXN0cnVjdCBwY2llX3BvcnQgKnBwID0gc3lzX3RvX3BjaWUoZGV2
LT5idXMtPnN5c2RhdGEpOw0KPiAtCWludCBpcnE7DQo+IC0NCj4gLQlpcnEgPSBvZl9pcnFfcGFy
c2VfYW5kX21hcF9wY2koZGV2LCBzbG90LCBwaW4pOw0KPiAtCWlmICghaXJxKQ0KPiAtCQlpcnEg
PSBwcC0+aXJxOw0KPiAtDQo+IC0JcmV0dXJuIGlycTsNCj4gLX0NCj4gLQ0KPiAtc3RhdGljIHN0
cnVjdCBod19wY2kgZHdfcGNpID0gew0KPiAtCS5zZXR1cAkJPSBkd19wY2llX3NldHVwLA0KPiAt
CS5zY2FuCQk9IGR3X3BjaWVfc2Nhbl9idXMsDQo+IC0JLm1hcF9pcnEJPSBkd19wY2llX21hcF9p
cnEsDQo+IC19Ow0KPiAtDQo+ICB2b2lkIGR3X3BjaWVfc2V0dXBfcmMoc3RydWN0IHBjaWVfcG9y
dCAqcHApDQo+ICB7DQo+ICAJdTMyIHZhbDsNCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2hv
c3QvcGNpZS1kZXNpZ253YXJlLmgNCj4gYi9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2Fy
ZS5oDQo+IGluZGV4IGQwYmJkMjcuLmFiNzg3MTAgMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvcGNp
L2hvc3QvcGNpZS1kZXNpZ253YXJlLmgNCj4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRl
c2lnbndhcmUuaA0KPiBAQCAtMzQsNyArMzQsNyBAQCBzdHJ1Y3QgcGNpZV9wb3J0IHsNCj4gIAl1
NjQJCQljZmcxX21vZF9iYXNlOw0KPiAgCXZvaWQgX19pb21lbQkJKnZhX2NmZzFfYmFzZTsNCj4g
IAl1MzIJCQljZmcxX3NpemU7DQo+IC0JdTY0CQkJaW9fYmFzZTsNCj4gKwlyZXNvdXJjZV9zaXpl
X3QJCQlpb19iYXNlOw0KPiAgCXU2NAkJCWlvX21vZF9iYXNlOw0KPiAgCXBoeXNfYWRkcl90CQlp
b19idXNfYWRkcjsNCj4gIAl1MzIJCQlpb19zaXplOw0KPiBAQCAtNDIsMTAgKzQyLDEwIEBAIHN0
cnVjdCBwY2llX3BvcnQgew0KPiAgCXU2NAkJCW1lbV9tb2RfYmFzZTsNCj4gIAlwaHlzX2FkZHJf
dAkJbWVtX2J1c19hZGRyOw0KPiAgCXUzMgkJCW1lbV9zaXplOw0KPiAtCXN0cnVjdCByZXNvdXJj
ZQkJY2ZnOw0KPiAtCXN0cnVjdCByZXNvdXJjZQkJaW87DQo+IC0Jc3RydWN0IHJlc291cmNlCQlt
ZW07DQo+IC0Jc3RydWN0IHJlc291cmNlCQlidXNuOw0KPiArCXN0cnVjdCByZXNvdXJjZQkJKmNm
ZzsNCj4gKwlzdHJ1Y3QgcmVzb3VyY2UJCSppbzsNCj4gKwlzdHJ1Y3QgcmVzb3VyY2UJCSptZW07
DQo+ICsJc3RydWN0IHJlc291cmNlCQkqYnVzbjsNCj4gIAlpbnQJCQlpcnE7DQo+ICAJdTMyCQkJ
bGFuZXM7DQo+ICAJc3RydWN0IHBjaWVfaG9zdF9vcHMJKm9wczsNCj4gZGlmZiAtLWdpdCBhL2Ry
aXZlcnMvcGNpL2hvc3QvcGNpZS1zcGVhcjEzeHguYyBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpZS0N
Cj4gc3BlYXIxM3h4LmMNCj4gaW5kZXggMDIwZDc4OC4uZTc4ZGRmOCAxMDA2NDQNCj4gLS0tIGEv
ZHJpdmVycy9wY2kvaG9zdC9wY2llLXNwZWFyMTN4eC5jDQo+ICsrKyBiL2RyaXZlcnMvcGNpL2hv
c3QvcGNpZS1zcGVhcjEzeHguYw0KPiBAQCAtMjg3LDcgKzI4Nyw3IEBAIHN0YXRpYyBpbnQgc3Bl
YXIxM3h4X2FkZF9wY2llX3BvcnQoc3RydWN0IHBjaWVfcG9ydA0KPiAqcHAsDQo+ICAJCXJldHVy
biByZXQ7DQo+ICAJfQ0KPiANCj4gLQlwcC0+cm9vdF9idXNfbnIgPSAtMTsNCj4gKwlwcC0+cm9v
dF9idXNfbnIgPSAwOw0KPiAgCXBwLT5vcHMgPSAmc3BlYXIxM3h4X3BjaWVfaG9zdF9vcHM7DQo+
IA0KPiAgCXJldCA9IGR3X3BjaWVfaG9zdF9pbml0KHBwKTsNCj4gLS0NCj4gMS45LjENCg0K

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[James Morse]

Zhou Wang wrote:
> I tested this patch on D02 board of Hisilicon. It works well.
> I have compiled the driver with multi_v7_defconfig. However, I don't
> have
> ARM32 PCIe related board to do test. It will be appreciated if someone
> could
> help to test it.
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> Tested-by: James Morse <james.morse@arm.com>

Tests on this new series, using the same i.MX 6Quad board, are not working.

The network card is no longer detected, and I get a lockup when removing
the root bridge and rescanning.

Partial dmesg output below. Significantly, the lines:
> [    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
> [    0.152142]   No bus range found for /soc/pcie@0x01000000, using [bus
00-ff]
are new.

Both series are applied to v4.1, use the same .config file, and the same dtb.
I will investigate further.

(Re-testing v2 works, so this isn't an interim hardware failure)

Thanks,

James



root@localhost:~# dmesg | grep -i pci
[    0.126184] PCI: CLS 0 bytes, default 64
[    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
[    0.152142]   No bus range found for /soc/pcie@0x01000000, using [bus 00-ff]
[    0.154183] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus 0000:00
[    0.154201] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.154215] pci_bus 0000:00: root bus resource [???
0x01f00000-0x01f7ffff flags 0x0]
[    0.154228] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.154270] pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
[    0.154306] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[    0.154333] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[    0.154352] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[    0.154377] pci 0000:00:00.0: IOMMU is currently not supported for PCI
[    0.154429] pci 0000:00:00.0: supports D1
[    0.154440] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[    0.154683] PCI: bus0: Fast back to back transfers disabled
[    0.154806] PCI: bus1: Fast back to back transfers enabled
[    0.154884] pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
[    0.154903] pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-0x0110ffff
pref]
[    0.154917] pci 0000:00:00.0: PCI bridge to [bus 01]
[    0.155145] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[    0.155161] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[    0.155279] aer 0000:00:00.0:pcie02: service driver aer loaded
[    1.188840] ehci-pci: EHCI PCI platform driver
[    1.232518] ohci-pci: OHCI PCI platform driver

RE: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Gabriele Paoloni]

PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBsaW51eC1wY2ktb3duZXJAdmdl
ci5rZXJuZWwub3JnIFttYWlsdG86bGludXgtcGNpLQ0KPiBvd25lckB2Z2VyLmtlcm5lbC5vcmdd
IE9uIEJlaGFsZiBPZiBKYW1lcyBNb3JzZQ0KPiBTZW50OiBXZWRuZXNkYXksIEp1bHkgMDEsIDIw
MTUgMzoyNyBQTQ0KPiBUbzogR2FicmllbGUgUGFvbG9uaTsgV2FuZ3pob3UgKEIpOyBCam9ybiBI
ZWxnYWFzOyBKaW5nb28gSGFuOyBQcmF0eXVzaA0KPiBBbmFuZDsgQXJuZCBCZXJnbWFubjsgTGl2
aXUgRHVkYXU7IGtpc2hvbkB0aS5jb207IHhvYnNAa29zYWdpLmNvbTsgbS0NCj4ga2FyaWNoZXJp
MkB0aS5jb207IE1pbmdodWFuLkxpYW5AZnJlZXNjYWxlLmNvbQ0KPiBDYzogbGludXgtcGNpQHZn
ZXIua2VybmVsLm9yZzsgbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnOw0KPiBk
ZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZzsgWXVhbnpoaWNoYW5nOyBaaHVkYWNhaTsgemhhbmdq
dWt1bzsNCj4gcWl1emhlbmZhOyBMaWd1b3podSAoS2VubmV0aCkNCj4gU3ViamVjdDogUmU6IFtQ
QVRDSCB2MyAyLzVdIFBDSTogZGVzaWdud2FyZTogQWRkIEFSTTY0IHN1cHBvcnQNCj4gDQo+IFpo
b3UgV2FuZyB3cm90ZToNCj4gPiBJIHRlc3RlZCB0aGlzIHBhdGNoIG9uIEQwMiBib2FyZCBvZiBI
aXNpbGljb24uIEl0IHdvcmtzIHdlbGwuDQo+ID4gSSBoYXZlIGNvbXBpbGVkIHRoZSBkcml2ZXIg
d2l0aCBtdWx0aV92N19kZWZjb25maWcuIEhvd2V2ZXIsIEkgZG9uJ3QNCj4gPiBoYXZlDQo+ID4g
QVJNMzIgUENJZSByZWxhdGVkIGJvYXJkIHRvIGRvIHRlc3QuIEl0IHdpbGwgYmUgYXBwcmVjaWF0
ZWQgaWYNCj4gc29tZW9uZQ0KPiA+IGNvdWxkDQo+ID4gaGVscCB0byB0ZXN0IGl0Lg0KPiA+DQo+
ID4gU2lnbmVkLW9mZi1ieTogWmhvdSBXYW5nIDx3YW5nemhvdTFAaGlzaWxpY29uLmNvbT4NCj4g
PiBTaWduZWQtb2ZmLWJ5OiBBcm5kIEJlcmdtYW5uIDxhcm5kQGFybmRiLmRlPg0KPiA+IFNpZ25l
ZC1vZmYtYnk6IEdhYnJpZWxlIFBhb2xvbmkgPGdhYnJpZWxlLnBhb2xvbmlAaHVhd2VpLmNvbT4N
Cj4gPiBUZXN0ZWQtYnk6IEZhYnJpY2UgR2FzbmllciA8ZmFicmljZS5nYXNuaWVyQHN0LmNvbT4N
Cj4gPiBUZXN0ZWQtYnk6IEphbWVzIE1vcnNlIDxqYW1lcy5tb3JzZUBhcm0uY29tPg0KPiANCj4g
VGVzdHMgb24gdGhpcyBuZXcgc2VyaWVzLCB1c2luZyB0aGUgc2FtZSBpLk1YIDZRdWFkIGJvYXJk
LCBhcmUgbm90DQo+IHdvcmtpbmcuDQo+IA0KPiBUaGUgbmV0d29yayBjYXJkIGlzIG5vIGxvbmdl
ciBkZXRlY3RlZCwgYW5kIEkgZ2V0IGEgbG9ja3VwIHdoZW4NCj4gcmVtb3ZpbmcNCj4gdGhlIHJv
b3QgYnJpZGdlIGFuZCByZXNjYW5uaW5nLg0KPiANCj4gUGFydGlhbCBkbWVzZyBvdXRwdXQgYmVs
b3cuIFNpZ25pZmljYW50bHksIHRoZSBsaW5lczoNCj4gPiBbICAgIDAuMTUyMTI4XSBQQ0kgaG9z
dCBicmlkZ2UgL3NvYy9wY2llQDB4MDEwMDAwMDAgcmFuZ2VzOg0KPiA+IFsgICAgMC4xNTIxNDJd
ICAgTm8gYnVzIHJhbmdlIGZvdW5kIGZvciAvc29jL3BjaWVAMHgwMTAwMDAwMCwgdXNpbmcNCj4g
W2J1cw0KPiAwMC1mZl0NCj4gYXJlIG5ldy4NCj4gDQo+IEJvdGggc2VyaWVzIGFyZSBhcHBsaWVk
IHRvIHY0LjEsIHVzZSB0aGUgc2FtZSAuY29uZmlnIGZpbGUsIGFuZCB0aGUNCj4gc2FtZSBkdGIu
DQo+IEkgd2lsbCBpbnZlc3RpZ2F0ZSBmdXJ0aGVyLg0KPiANCj4gKFJlLXRlc3RpbmcgdjIgd29y
a3MsIHNvIHRoaXMgaXNuJ3QgYW4gaW50ZXJpbSBoYXJkd2FyZSBmYWlsdXJlKQ0KDQpUaGlzIGlz
IGEgYml0IHdlaXJkLi4uLg0KDQpQYXRjaCAyLzUgaXMgdGhlIG9ubHkgb25lIHRoYXQgYWZmZWN0
IHBsYXRmb3JtcyBkaWZmZXJlbnQgZnJvbSBIaXNpbGljb24NCg0KVGhlIG9ubHkgZGlmZmVyZW5j
ZSBiZXR3ZWVuIFYzIHBhdGNoWzIvNV0gYW5kIHYyIHBhdGNoWzIvNF0gaXMNCg0KKioqKioqKioq
KioqKg0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLWtleXN0b25lLWR3LmMgYi9k
cml2ZXJzL3BjaS9ob3N0L3BjaS1rZXlzdG9uZS1kdy5jDQppbmRleCBmMzQ4OTJlLi5iMWU0MTM1
IDEwMDY0NA0KLS0tIGEvZHJpdmVycy9wY2kvaG9zdC9wY2kta2V5c3RvbmUtZHcuYw0KKysrIGIv
ZHJpdmVycy9wY2kvaG9zdC9wY2kta2V5c3RvbmUtZHcuYw0KQEAgLTMyNyw3ICszMjcsNyBAQCBz
dGF0aWMgdm9pZCBrc19kd19wY2llX2NsZWFyX2RiaV9tb2RlKHZvaWQgX19pb21lbSAqcmVnX3Zp
cnQpDQogdm9pZCBrc19kd19wY2llX3NldHVwX3JjX2FwcF9yZWdzKHN0cnVjdCBrZXlzdG9uZV9w
Y2llICprc19wY2llKQ0KIHsNCiAJc3RydWN0IHBjaWVfcG9ydCAqcHAgPSAma3NfcGNpZS0+cHA7
DQotCXUzMiBzdGFydCA9IHBwLT5tZW0uc3RhcnQsIGVuZCA9IHBwLT5tZW0uZW5kOw0KKwl1MzIg
c3RhcnQgPSBwcC0+bWVtLT5zdGFydCwgZW5kID0gcHAtPm1lbS0+ZW5kOw0KIAlpbnQgaSwgdHJf
c2l6ZTsNCiANCiAJLyogRGlzYWJsZSBCQVJzIGZvciBpbmJvdW5kIGFjY2VzcyAqLw0KKioqKioq
KioqKioqKioNClRoYXQgaXMgcHJlc2VudCBpbiB2MyBidXQgbm90IGluIHYyLiBBbmQgaXQgc2hv
dWxkIGFmZmVjdCBrZXlzdG9uZSBvbmx5Li4uLnNvIHVzaW5nIHBhdGNoIHYzIG9uIHRoZSBzYW1l
IGJyYW5jaCB3aGVyZSB5b3UgYXBwbGllZCBwYXRjaCB2MiBJIHdvdWxkIGV4cGVjdCB0aGUgc2Ft
ZSByZXN1bHRzLi4uDQoNCj4gDQo+IFRoYW5rcywNCj4gDQo+IEphbWVzDQo+IA0KPiANCj4gDQo+
IHJvb3RAbG9jYWxob3N0On4jIGRtZXNnIHwgZ3JlcCAtaSBwY2kNCj4gWyAgICAwLjEyNjE4NF0g
UENJOiBDTFMgMCBieXRlcywgZGVmYXVsdCA2NA0KPiBbICAgIDAuMTUyMTI4XSBQQ0kgaG9zdCBi
cmlkZ2UgL3NvYy9wY2llQDB4MDEwMDAwMDAgcmFuZ2VzOg0KPiBbICAgIDAuMTUyMTQyXSAgIE5v
IGJ1cyByYW5nZSBmb3VuZCBmb3IgL3NvYy9wY2llQDB4MDEwMDAwMDAsIHVzaW5nDQo+IFtidXMg
MDAtZmZdDQo+IFsgICAgMC4xNTQxODNdIGlteDZxLXBjaWUgMWZmYzAwMC5wY2llOiBQQ0kgaG9z
dCBicmlkZ2UgdG8gYnVzIDAwMDA6MDANCj4gWyAgICAwLjE1NDIwMV0gcGNpX2J1cyAwMDAwOjAw
OiByb290IGJ1cyByZXNvdXJjZSBbYnVzIDAwLWZmXQ0KPiBbICAgIDAuMTU0MjE1XSBwY2lfYnVz
IDAwMDA6MDA6IHJvb3QgYnVzIHJlc291cmNlIFs/Pz8NCj4gMHgwMWYwMDAwMC0weDAxZjdmZmZm
IGZsYWdzIDB4MF0NCj4gWyAgICAwLjE1NDIyOF0gcGNpX2J1cyAwMDAwOjAwOiByb290IGJ1cyBy
ZXNvdXJjZSBbaW8gIDB4MDAwMC0weGZmZmZdDQo+IFsgICAgMC4xNTQyNzBdIHBjaV9idXMgMDAw
MDowMDogcm9vdCBidXMgcmVzb3VyY2UgW21lbSAweDAxMDAwMDAwLQ0KPiAweDAxZWZmZmZmXQ0K
PiBbICAgIDAuMTU0MzA2XSBwY2kgMDAwMDowMDowMC4wOiBbMTZjMzphYmNkXSB0eXBlIDAxIGNs
YXNzIDB4MDYwNDAwDQo+IFsgICAgMC4xNTQzMzNdIHBjaSAwMDAwOjAwOjAwLjA6IHJlZyAweDEw
OiBbbWVtIDB4MDAwMDAwMDAtMHgwMDBmZmZmZl0NCj4gWyAgICAwLjE1NDM1Ml0gcGNpIDAwMDA6
MDA6MDAuMDogcmVnIDB4Mzg6IFttZW0gMHgwMDAwMDAwMC0weDAwMDBmZmZmDQo+IHByZWZdDQo+
IFsgICAgMC4xNTQzNzddIHBjaSAwMDAwOjAwOjAwLjA6IElPTU1VIGlzIGN1cnJlbnRseSBub3Qg
c3VwcG9ydGVkIGZvcg0KPiBQQ0kNCj4gWyAgICAwLjE1NDQyOV0gcGNpIDAwMDA6MDA6MDAuMDog
c3VwcG9ydHMgRDENCj4gWyAgICAwLjE1NDQ0MF0gcGNpIDAwMDA6MDA6MDAuMDogUE1FIyBzdXBw
b3J0ZWQgZnJvbSBEMCBEMSBEM2hvdCBEM2NvbGQNCj4gWyAgICAwLjE1NDY4M10gUENJOiBidXMw
OiBGYXN0IGJhY2sgdG8gYmFjayB0cmFuc2ZlcnMgZGlzYWJsZWQNCj4gWyAgICAwLjE1NDgwNl0g
UENJOiBidXMxOiBGYXN0IGJhY2sgdG8gYmFjayB0cmFuc2ZlcnMgZW5hYmxlZA0KPiBbICAgIDAu
MTU0ODg0XSBwY2kgMDAwMDowMDowMC4wOiBCQVIgMDogYXNzaWduZWQgW21lbSAweDAxMDAwMDAw
LQ0KPiAweDAxMGZmZmZmXQ0KPiBbICAgIDAuMTU0OTAzXSBwY2kgMDAwMDowMDowMC4wOiBCQVIg
NjogYXNzaWduZWQgW21lbSAweDAxMTAwMDAwLQ0KPiAweDAxMTBmZmZmDQo+IHByZWZdDQo+IFsg
ICAgMC4xNTQ5MTddIHBjaSAwMDAwOjAwOjAwLjA6IFBDSSBicmlkZ2UgdG8gW2J1cyAwMV0NCj4g
WyAgICAwLjE1NTE0NV0gcGNpZXBvcnQgMDAwMDowMDowMC4wOiBTaWduYWxpbmcgUE1FIHRocm91
Z2ggUENJZSBQTUUNCj4gaW50ZXJydXB0DQo+IFsgICAgMC4xNTUxNjFdIHBjaWVfcG1lIDAwMDA6
MDA6MDAuMDpwY2llMDE6IHNlcnZpY2UgZHJpdmVyIHBjaWVfcG1lDQo+IGxvYWRlZA0KPiBbICAg
IDAuMTU1Mjc5XSBhZXIgMDAwMDowMDowMC4wOnBjaWUwMjogc2VydmljZSBkcml2ZXIgYWVyIGxv
YWRlZA0KPiBbICAgIDEuMTg4ODQwXSBlaGNpLXBjaTogRUhDSSBQQ0kgcGxhdGZvcm0gZHJpdmVy
DQo+IFsgICAgMS4yMzI1MThdIG9oY2ktcGNpOiBPSENJIFBDSSBwbGF0Zm9ybSBkcml2ZXINCj4g
DQo+IC0tDQo+IFRvIHVuc3Vic2NyaWJlIGZyb20gdGhpcyBsaXN0OiBzZW5kIHRoZSBsaW5lICJ1
bnN1YnNjcmliZSBsaW51eC1wY2kiIGluDQo+IHRoZSBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpv
cmRvbW9Admdlci5rZXJuZWwub3JnDQo+IE1vcmUgbWFqb3Jkb21vIGluZm8gYXQgIGh0dHA6Ly92
Z2VyLmtlcm5lbC5vcmcvbWFqb3Jkb21vLWluZm8uaHRtbA0K

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[James Morse]

Gabriele Paoloni wrote:
>> Both series are applied to v4.1, use the same .config file, and the
>> same dtb.
>> I will investigate further.
>>
>> (Re-testing v2 works, so this isn't an interim hardware failure)
>
> This is a bit weird....
>
> Patch 2/5 is the only one that affect platforms different from Hisilicon
>
> The only difference between V3 patch[2/5] and v2 patch[2/4] is

Between v3:2/5 and your replacement for v2:2/4, which arrived after I had
tested the v2 series. As the patch has been replaced with a different one -
neither 'tested-by' is true any more.

It looks like the BAR containing the bridge window is not being assigned,
so no devices on bus 1 are discovered.

I will send the full v2 and v3 dmesg output separately.


Thanks,

James

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Zhou Wang]

On 2015/7/1 21:29, Gabriele Paoloni wrote:
> Adding to the recipients list the authors of the drivers that depend on Synopsys Designware and that are not included
> 
> Respectively:
> pci-dra7xx Kishon Vijay Abraham I <kishon@ti.com>
> pci-imx6 Sean Cross <xobs@kosagi.com>
> pci-keystone Murali Karicheri <m-karicheri2@ti.com>
> pci-layerscape Minghuan Lian <Minghuan.Lian@freescale.com>
> 
> Driver Authors already included:
> pci-exynos Jingoo Han <jg1.han@samsung.com>
> pcie-spear13xx Pratyush Anand <pratyush.anand@st.com>
> 
> Cheers
> 
> Gab
> 

Hi Gab,

Many thanks for adding the related guys.

Regards,
Zhou

>> -----Original Message-----
>> From: Wangzhou (B)
>> Sent: Wednesday, July 01, 2015 10:44 AM
>> To: Bjorn Helgaas; Jingoo Han; Pratyush Anand; Arnd Bergmann; Gabriele
>> Paoloni; James Morse; Liviu Dudau
>> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo;
>> qiuzhenfa; Liguozhu (Kenneth); Wangzhou (B)
>> Subject: [PATCH v3 2/5] PCI: designware: Add ARM64 support
>>
>> This patch tries to unify ARM32 and ARM64 PCIe in designware driver.
>> Delete
>> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct
>> hw_pci,
>> move related operations to dw_pcie_host_init. Also set pp->root_bus_nr
>> = 0 in
>> each PCIe host driver which is based on pcie-designware. This patch
>> also try
>> to use of_pci_get_host_bridge_resources for ARM32 and ARM64 according
>> to the
>> suggestion for Gabriele[1]
>>
>> I tested this patch on D02 board of Hisilicon. It works well.
>> I have compiled the driver with multi_v7_defconfig. However, I don't
>> have
>> ARM32 PCIe related board to do test. It will be appreciated if someone
>> could
>> help to test it.
>>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
>> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>> Tested-by: James Morse <james.morse@arm.com>
>>
>> [1] http://www.spinics.net/lists/linux-pci/msg42194.html
>> ---
>>  drivers/pci/host/pci-dra7xx.c      |   1 +
>>  drivers/pci/host/pci-exynos.c      |   2 +-
>>  drivers/pci/host/pci-imx6.c        |   2 +-
>>  drivers/pci/host/pci-keystone-dw.c |   2 +-
>>  drivers/pci/host/pci-keystone.c    |   2 +-
>>  drivers/pci/host/pci-layerscape.c  |   2 +-
>>  drivers/pci/host/pcie-designware.c | 242 +++++++++++++++--------------
>> --------
>>  drivers/pci/host/pcie-designware.h |  10 +-
>>  drivers/pci/host/pcie-spear13xx.c  |   2 +-
>>  9 files changed, 110 insertions(+), 155 deletions(-)
>>
>> diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-
>> dra7xx.c
>> index 2d57e19..5c8b6ab 100644
>> --- a/drivers/pci/host/pci-dra7xx.c
>> +++ b/drivers/pci/host/pci-dra7xx.c
>> @@ -280,6 +280,7 @@ static int __init dra7xx_add_pcie_port(struct
>> dra7xx_pcie *dra7xx,
>>
>>  	pp = &dra7xx->pp;
>>  	pp->dev = dev;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &dra7xx_pcie_host_ops;
>>
>>  	pp->irq = platform_get_irq(pdev, 1);
>> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-
>> exynos.c
>> index c139237..4b6db6c 100644
>> --- a/drivers/pci/host/pci-exynos.c
>> +++ b/drivers/pci/host/pci-exynos.c
>> @@ -534,7 +534,7 @@ static int __init exynos_add_pcie_port(struct
>> pcie_port *pp,
>>  		}
>>  	}
>>
>> -	pp->root_bus_nr = -1;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &exynos_pcie_host_ops;
>>
>>  	ret = dw_pcie_host_init(pp);
>> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
>> index fdb9536..c4a80c5 100644
>> --- a/drivers/pci/host/pci-imx6.c
>> +++ b/drivers/pci/host/pci-imx6.c
>> @@ -541,7 +541,7 @@ static int __init imx6_add_pcie_port(struct
>> pcie_port *pp,
>>  		}
>>  	}
>>
>> -	pp->root_bus_nr = -1;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &imx6_pcie_host_ops;
>>
>>  	ret = dw_pcie_host_init(pp);
>> diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-
>> keystone-dw.c
>> index f34892e..b1e4135 100644
>> --- a/drivers/pci/host/pci-keystone-dw.c
>> +++ b/drivers/pci/host/pci-keystone-dw.c
>> @@ -327,7 +327,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem
>> *reg_virt)
>>  void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
>>  {
>>  	struct pcie_port *pp = &ks_pcie->pp;
>> -	u32 start = pp->mem.start, end = pp->mem.end;
>> +	u32 start = pp->mem->start, end = pp->mem->end;
>>  	int i, tr_size;
>>
>>  	/* Disable BARs for inbound access */
>> diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-
>> keystone.c
>> index 75333b0..df91f5e 100644
>> --- a/drivers/pci/host/pci-keystone.c
>> +++ b/drivers/pci/host/pci-keystone.c
>> @@ -312,7 +312,7 @@ static int __init ks_add_pcie_port(struct
>> keystone_pcie *ks_pcie,
>>  			return ret;
>>  	}
>>
>> -	pp->root_bus_nr = -1;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &keystone_pcie_host_ops;
>>  	ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
>>  	if (ret) {
>> diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-
>> layerscape.c
>> index 4a6e62f..5c7a9c4 100644
>> --- a/drivers/pci/host/pci-layerscape.c
>> +++ b/drivers/pci/host/pci-layerscape.c
>> @@ -101,7 +101,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie)
>>  	pp = &pcie->pp;
>>  	pp->dev = pcie->dev;
>>  	pp->dbi_base = pcie->dbi;
>> -	pp->root_bus_nr = -1;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &ls_pcie_host_ops;
>>
>>  	ret = dw_pcie_host_init(pp);
>> diff --git a/drivers/pci/host/pcie-designware.c
>> b/drivers/pci/host/pcie-designware.c
>> index 2e9f84f..844febee 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -11,6 +11,7 @@
>>   * published by the Free Software Foundation.
>>   */
>>
>> +#include <linux/hardirq.h>
>>  #include <linux/irq.h>
>>  #include <linux/irqdomain.h>
>>  #include <linux/kernel.h>
>> @@ -67,16 +68,7 @@
>>  #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
>>  #define PCIE_ATU_UPPER_TARGET		0x91C
>>
>> -static struct hw_pci dw_pci;
>> -
>> -static unsigned long global_io_offset;
>> -
>> -static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>> -{
>> -	BUG_ON(!sys->private_data);
>> -
>> -	return sys->private_data;
>> -}
>> +static struct pci_ops dw_pcie_ops;
>>
>>  int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>>  {
>> @@ -238,7 +230,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port
>> *pp, int irq)
>>  static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
>>  {
>>  	int irq, pos0, i;
>> -	struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
>> +	struct pcie_port *pp = desc->dev->bus->sysdata;
>>
>>  	pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
>>  				       order_base_2(no_irqs));
>> @@ -281,7 +273,7 @@ static int dw_msi_setup_irq(struct msi_controller
>> *chip, struct pci_dev *pdev,
>>  {
>>  	int irq, pos;
>>  	struct msi_msg msg;
>> -	struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
>> +	struct pcie_port *pp = pdev->bus->sysdata;
>>
>>  	if (desc->msi_attrib.is_msix)
>>  		return -EINVAL;
>> @@ -310,7 +302,7 @@ static void dw_msi_teardown_irq(struct
>> msi_controller *chip, unsigned int irq)
>>  {
>>  	struct irq_data *data = irq_get_irq_data(irq);
>>  	struct msi_desc *msi = irq_data_get_msi(data);
>> -	struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
>> +	struct pcie_port *pp = msi->dev->bus->sysdata;
>>
>>  	clear_irq_range(pp, irq, 1, data->hwirq);
>>  }
>> @@ -342,16 +334,24 @@ static const struct irq_domain_ops msi_domain_ops
>> = {
>>  	.map = dw_pcie_msi_map,
>>  };
>>
>> -int dw_pcie_host_init(struct pcie_port *pp)
>> +int __init dw_pcie_host_init(struct pcie_port *pp)
>>  {
>>  	struct device_node *np = pp->dev->of_node;
>>  	struct platform_device *pdev = to_platform_device(pp->dev);
>> -	struct of_pci_range range;
>> -	struct of_pci_range_parser parser;
>> +	struct pci_bus *bus;
>>  	struct resource *cfg_res;
>> +	LIST_HEAD(res);
>>  	u32 val, na, ns;
>>  	const __be32 *addrp;
>>  	int i, index, ret;
>> +	int rlen;
>> +	struct resource_entry *win;
>> +	const __be32 *parser_range_end = of_get_property(np, "ranges",
>> &rlen);
>> +
>> +	if (parser_range_end == NULL)
>> +			return -ENOENT;
>> +	parser_range_end += rlen/sizeof(__be32);
>> +
>>
>>  	/* Find the address cell size and the number of cells in order to
>> get
>>  	 * the untranslated address.
>> @@ -375,78 +375,67 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>  		dev_err(pp->dev, "missing *config* reg space\n");
>>  	}
>>
>> -	if (of_pci_range_parser_init(&parser, np)) {
>> -		dev_err(pp->dev, "missing ranges property\n");
>> -		return -EINVAL;
>> -	}
>> +	ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp-
>>> io_base);
>> +	if (ret)
>> +		return ret;
>>
>>  	/* Get the I/O and memory ranges from DT */
>> -	for_each_of_pci_range(&parser, &range) {
>> -		unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
>> -
>> -		if (restype == IORESOURCE_IO) {
>> -			of_pci_range_to_resource(&range, np, &pp->io);
>> -			pp->io.name = "I/O";
>> -			pp->io.start = max_t(resource_size_t,
>> -					     PCIBIOS_MIN_IO,
>> -					     range.pci_addr + global_io_offset);
>> -			pp->io.end = min_t(resource_size_t,
>> -					   IO_SPACE_LIMIT,
>> -					   range.pci_addr + range.size
>> -					   + global_io_offset - 1);
>> -			pp->io_size = resource_size(&pp->io);
>> -			pp->io_bus_addr = range.pci_addr;
>> -			pp->io_base = range.cpu_addr;
>> -
>> -			/* Find the untranslated IO space address */
>> -			pp->io_mod_base = of_read_number(parser.range -
>> -							 parser.np + na, ns);
>> -		}
>> -		if (restype == IORESOURCE_MEM) {
>> -			of_pci_range_to_resource(&range, np, &pp->mem);
>> -			pp->mem.name = "MEM";
>> -			pp->mem_size = resource_size(&pp->mem);
>> -			pp->mem_bus_addr = range.pci_addr;
>> -
>> -			/* Find the untranslated MEM space address */
>> -			pp->mem_mod_base = of_read_number(parser.range -
>> -							  parser.np + na, ns);
>> -		}
>> -		if (restype == 0) {
>> -			of_pci_range_to_resource(&range, np, &pp->cfg);
>> -			pp->cfg0_size = resource_size(&pp->cfg)/2;
>> -			pp->cfg1_size = resource_size(&pp->cfg)/2;
>> -			pp->cfg0_base = pp->cfg.start;
>> -			pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
>> +	resource_list_for_each_entry(win, &res) {
>> +		switch (resource_type(win->res)) {
>> +		case IORESOURCE_IO:
>> +			pp->io = win->res;
>> +			pp->io->name = "I/O";
>> +			pp->io_size = resource_size(pp->io);
>> +			pp->io_bus_addr = pp->io->start - win->offset;
>> +			/* magic 5 below comes from magic na and ns in
>> +			 * of_pci_range_parser_init()                 */
>> +			pp->io_mod_base = of_read_number(parser_range_end -
>> +					of_n_addr_cells(np) - 5 + na, ns);
>> +			ret = pci_remap_iospace(pp->io, pp->io_base);
>> +			if (ret) {
>> +				dev_warn(pp->dev, "error %d: failed to map
>> resource %pR\n",
>> +				ret, pp->io);
>> +			continue;
>> +			}
>> +			break;
>> +		case IORESOURCE_MEM:
>> +			pp->mem = win->res;
>> +			pp->mem->name = "MEM";
>> +			pp->mem_size = resource_size(pp->mem);
>> +			pp->mem_bus_addr = pp->mem->start - win->offset;
>> +			pp->mem_mod_base = of_read_number(parser_range_end -
>> +					of_n_addr_cells(np) - 5 + na, ns);
>> +			break;
>> +		case 0:
>> +			pp->cfg = win->res;
>> +			pp->cfg0_size = resource_size(pp->cfg)/2;
>> +			pp->cfg1_size = resource_size(pp->cfg)/2;
>> +			pp->cfg0_base = pp->cfg->start;
>> +			pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
>>
>>  			/* Find the untranslated configuration space address
>> */
>> -			pp->cfg0_mod_base = of_read_number(parser.range -
>> -							   parser.np + na, ns);
>> -			pp->cfg1_mod_base = pp->cfg0_mod_base +
>> -					    pp->cfg0_size;
>> +			pp->cfg0_mod_base = of_read_number(parser_range_end -
>> +					of_n_addr_cells(np) - 5 + na, ns);
>> +			pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
>> +			break;
>> +		case IORESOURCE_BUS:
>> +			pp->busn = win->res;
>> +			break;
>> +		default:
>> +			continue;
>>  		}
>>  	}
>>
>> -	ret = of_pci_parse_bus_range(np, &pp->busn);
>> -	if (ret < 0) {
>> -		pp->busn.name = np->name;
>> -		pp->busn.start = 0;
>> -		pp->busn.end = 0xff;
>> -		pp->busn.flags = IORESOURCE_BUS;
>> -		dev_dbg(pp->dev, "failed to parse bus-range property: %d,
>> using default %pR\n",
>> -			ret, &pp->busn);
>> -	}
>> -
>>  	if (!pp->dbi_base) {
>> -		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
>> -					resource_size(&pp->cfg));
>> +		pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
>> +					resource_size(pp->cfg));
>>  		if (!pp->dbi_base) {
>>  			dev_err(pp->dev, "error with ioremap\n");
>>  			return -ENOMEM;
>>  		}
>>  	}
>>
>> -	pp->mem_base = pp->mem.start;
>> +	pp->mem_base = pp->mem->start;
>>
>>  	if (!pp->va_cfg0_base) {
>>  		pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
>> @@ -493,24 +482,47 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>  	if (pp->ops->host_init)
>>  		pp->ops->host_init(pp);
>>
>> -	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>> +	if (dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0)
>> +			!= PCIBIOS_SUCCESSFUL)
>> +		return -EINVAL;
>>
>>  	/* program correct class for RC */
>> -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2,
>> PCI_CLASS_BRIDGE_PCI);
>> +	if (dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2,
>> PCI_CLASS_BRIDGE_PCI)
>> +			!= PCIBIOS_SUCCESSFUL)
>> +		return -EINVAL;
>> +
>> +	if (dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,
>> &val)
>> +			!= PCIBIOS_SUCCESSFUL)
>> +		return -EINVAL;
>>
>> -	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
>>  	val |= PORT_LOGIC_SPEED_CHANGE;
>> -	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
>>
>> -#ifdef CONFIG_PCI_MSI
>> -	dw_pcie_msi_chip.dev = pp->dev;
>> -	dw_pci.msi_ctrl = &dw_pcie_msi_chip;
>> +	if (dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val)
>> +			!= PCIBIOS_SUCCESSFUL)
>> +		return -EINVAL;
>> +
>> +	bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
>> +			      pp, &res);
>> +	if (!bus)
>> +		return -ENOMEM;
>> +
>> +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
>> +	bus->msi = container_of(&pp->irq_domain, struct msi_controller,
>> domain);
>> +#else
>> +	bus->msi = &dw_pcie_msi_chip;
>>  #endif
>>
>> -	dw_pci.nr_controllers = 1;
>> -	dw_pci.private_data = (void **)&pp;
>> +	pci_scan_child_bus(bus);
>> +	if (pp->ops->scan_bus)
>> +		pp->ops->scan_bus(pp);
>>
>> -	pci_common_init_dev(pp->dev, &dw_pci);
>> +#ifdef CONFIG_ARM
>> +	/* support old dtbs that incorrectly describe IRQs */
>> +	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
>> +#endif
>> +
>> +	pci_assign_unassigned_bus_resources(bus);
>> +	pci_bus_add_devices(bus);
>>
>>  	return 0;
>>  }
>> @@ -653,7 +665,7 @@ static int dw_pcie_valid_config(struct pcie_port
>> *pp,
>>  static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>>  			int size, u32 *val)
>>  {
>> -	struct pcie_port *pp = sys_to_pcie(bus->sysdata);
>> +	struct pcie_port *pp = bus->sysdata;
>>  	int ret;
>>
>>  	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
>> @@ -677,7 +689,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32
>> devfn, int where,
>>  static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>>  			int where, int size, u32 val)
>>  {
>> -	struct pcie_port *pp = sys_to_pcie(bus->sysdata);
>> +	struct pcie_port *pp = bus->sysdata;
>>  	int ret;
>>
>>  	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
>> @@ -701,64 +713,6 @@ static struct pci_ops dw_pcie_ops = {
>>  	.write = dw_pcie_wr_conf,
>>  };
>>
>> -static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
>> -{
>> -	struct pcie_port *pp;
>> -
>> -	pp = sys_to_pcie(sys);
>> -
>> -	if (global_io_offset < SZ_1M && pp->io_size > 0) {
>> -		sys->io_offset = global_io_offset - pp->io_bus_addr;
>> -		pci_ioremap_io(global_io_offset, pp->io_base);
>> -		global_io_offset += SZ_64K;
>> -		pci_add_resource_offset(&sys->resources, &pp->io,
>> -					sys->io_offset);
>> -	}
>> -
>> -	sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
>> -	pci_add_resource_offset(&sys->resources, &pp->mem, sys-
>>> mem_offset);
>> -	pci_add_resource(&sys->resources, &pp->busn);
>> -
>> -	return 1;
>> -}
>> -
>> -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data
>> *sys)
>> -{
>> -	struct pci_bus *bus;
>> -	struct pcie_port *pp = sys_to_pcie(sys);
>> -
>> -	pp->root_bus_nr = sys->busnr;
>> -	bus = pci_create_root_bus(pp->dev, sys->busnr,
>> -				  &dw_pcie_ops, sys, &sys->resources);
>> -	if (!bus)
>> -		return NULL;
>> -
>> -	pci_scan_child_bus(bus);
>> -
>> -	if (bus && pp->ops->scan_bus)
>> -		pp->ops->scan_bus(pp);
>> -
>> -	return bus;
>> -}
>> -
>> -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
>> -{
>> -	struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
>> -	int irq;
>> -
>> -	irq = of_irq_parse_and_map_pci(dev, slot, pin);
>> -	if (!irq)
>> -		irq = pp->irq;
>> -
>> -	return irq;
>> -}
>> -
>> -static struct hw_pci dw_pci = {
>> -	.setup		= dw_pcie_setup,
>> -	.scan		= dw_pcie_scan_bus,
>> -	.map_irq	= dw_pcie_map_irq,
>> -};
>> -
>>  void dw_pcie_setup_rc(struct pcie_port *pp)
>>  {
>>  	u32 val;
>> diff --git a/drivers/pci/host/pcie-designware.h
>> b/drivers/pci/host/pcie-designware.h
>> index d0bbd27..ab78710 100644
>> --- a/drivers/pci/host/pcie-designware.h
>> +++ b/drivers/pci/host/pcie-designware.h
>> @@ -34,7 +34,7 @@ struct pcie_port {
>>  	u64			cfg1_mod_base;
>>  	void __iomem		*va_cfg1_base;
>>  	u32			cfg1_size;
>> -	u64			io_base;
>> +	resource_size_t			io_base;
>>  	u64			io_mod_base;
>>  	phys_addr_t		io_bus_addr;
>>  	u32			io_size;
>> @@ -42,10 +42,10 @@ struct pcie_port {
>>  	u64			mem_mod_base;
>>  	phys_addr_t		mem_bus_addr;
>>  	u32			mem_size;
>> -	struct resource		cfg;
>> -	struct resource		io;
>> -	struct resource		mem;
>> -	struct resource		busn;
>> +	struct resource		*cfg;
>> +	struct resource		*io;
>> +	struct resource		*mem;
>> +	struct resource		*busn;
>>  	int			irq;
>>  	u32			lanes;
>>  	struct pcie_host_ops	*ops;
>> diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-
>> spear13xx.c
>> index 020d788..e78ddf8 100644
>> --- a/drivers/pci/host/pcie-spear13xx.c
>> +++ b/drivers/pci/host/pcie-spear13xx.c
>> @@ -287,7 +287,7 @@ static int spear13xx_add_pcie_port(struct pcie_port
>> *pp,
>>  		return ret;
>>  	}
>>
>> -	pp->root_bus_nr = -1;
>> +	pp->root_bus_nr = 0;
>>  	pp->ops = &spear13xx_pcie_host_ops;
>>
>>  	ret = dw_pcie_host_init(pp);
>> --
>> 1.9.1
> 

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Zhou Wang]

On 2015/7/2 1:32, James Morse wrote:
> Gabriele Paoloni wrote:
>>> Both series are applied to v4.1, use the same .config file, and the
>>> same dtb.
>>> I will investigate further.
>>>
>>> (Re-testing v2 works, so this isn't an interim hardware failure)
>>
>> This is a bit weird....
>>
>> Patch 2/5 is the only one that affect platforms different from Hisilicon
>>
>> The only difference between V3 patch[2/5] and v2 patch[2/4] is
> 
> Between v3:2/5 and your replacement for v2:2/4, which arrived after I had
> tested the v2 series. As the patch has been replaced with a different one -
> neither 'tested-by' is true any more.
>

Hi James,

Firstly, many thanks for your test!

Yes. v3:2/5 had merged Gabriele's codes in. So if you made test on original
v2 patchset and v3 patchset, I think the differences include Gabriele's codes
and codes in pci-keystone-dw.c.

As the patch has been replaced with a different one, I think I should have
added 'tested-by' after it passes your test, is this right?

> It looks like the BAR containing the bridge window is not being assigned,
> so no devices on bus 1 are discovered.
> 
> I will send the full v2 and v3 dmesg output separately.
> 

Thanks, I will debug the problem according your log.

Regards,
Zhou

> 
> Thanks,
> 
> James
> 
> 
> .
> 

RE: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Gabriele Paoloni]

DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogbGludXgtcGNpLW93bmVy
QHZnZXIua2VybmVsLm9yZyBbbWFpbHRvOmxpbnV4LXBjaS0NCj4gb3duZXJAdmdlci5rZXJuZWwu
b3JnXSBPbiBCZWhhbGYgT2YgSmFtZXMgTW9yc2UNCj4gU2VudDogMDEgSnVseSAyMDE1IDE4OjMz
DQo+IFRvOiBHYWJyaWVsZSBQYW9sb25pOyBXYW5nemhvdSAoQik7IEJqb3JuIEhlbGdhYXM7IEpp
bmdvbyBIYW47IFByYXR5dXNoDQo+IEFuYW5kOyBBcm5kIEJlcmdtYW5uOyBMaXZpdSBEdWRhdTsg
a2lzaG9uQHRpLmNvbTsgeG9ic0Brb3NhZ2kuY29tOyBtLQ0KPiBrYXJpY2hlcmkyQHRpLmNvbTsg
TWluZ2h1YW4uTGlhbkBmcmVlc2NhbGUuY29tDQo+IENjOiBsaW51eC1wY2lAdmdlci5rZXJuZWwu
b3JnOyBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7DQo+IGRldmljZXRyZWVA
dmdlci5rZXJuZWwub3JnOyBZdWFuemhpY2hhbmc7IFpodWRhY2FpOyB6aGFuZ2p1a3VvOw0KPiBx
aXV6aGVuZmE7IExpZ3Vvemh1IChLZW5uZXRoKQ0KPiBTdWJqZWN0OiBSZTogW1BBVENIIHYzIDIv
NV0gUENJOiBkZXNpZ253YXJlOiBBZGQgQVJNNjQgc3VwcG9ydA0KPiANCj4gR2FicmllbGUgUGFv
bG9uaSB3cm90ZToNCj4gPj4gQm90aCBzZXJpZXMgYXJlIGFwcGxpZWQgdG8gdjQuMSwgdXNlIHRo
ZSBzYW1lIC5jb25maWcgZmlsZSwgYW5kIHRoZQ0KPiA+PiBzYW1lIGR0Yi4NCj4gPj4gSSB3aWxs
IGludmVzdGlnYXRlIGZ1cnRoZXIuDQo+ID4+DQo+ID4+IChSZS10ZXN0aW5nIHYyIHdvcmtzLCBz
byB0aGlzIGlzbid0IGFuIGludGVyaW0gaGFyZHdhcmUgZmFpbHVyZSkNCj4gPg0KPiA+IFRoaXMg
aXMgYSBiaXQgd2VpcmQuLi4uDQo+ID4NCj4gPiBQYXRjaCAyLzUgaXMgdGhlIG9ubHkgb25lIHRo
YXQgYWZmZWN0IHBsYXRmb3JtcyBkaWZmZXJlbnQgZnJvbQ0KPiBIaXNpbGljb24NCj4gPg0KPiA+
IFRoZSBvbmx5IGRpZmZlcmVuY2UgYmV0d2VlbiBWMyBwYXRjaFsyLzVdIGFuZCB2MiBwYXRjaFsy
LzRdIGlzDQo+IA0KPiBCZXR3ZWVuIHYzOjIvNSBhbmQgeW91ciByZXBsYWNlbWVudCBmb3IgdjI6
Mi80LCB3aGljaCBhcnJpdmVkIGFmdGVyIEkNCj4gaGFkDQo+IHRlc3RlZCB0aGUgdjIgc2VyaWVz
LiBBcyB0aGUgcGF0Y2ggaGFzIGJlZW4gcmVwbGFjZWQgd2l0aCBhIGRpZmZlcmVudA0KPiBvbmUg
LQ0KPiBuZWl0aGVyICd0ZXN0ZWQtYnknIGlzIHRydWUgYW55IG1vcmUuDQoNClNvcnJ5IEkgbWlz
cmVhZCB5b3VyIHByZXZpb3VzIGVtYWlsDQoNCj4gDQo+IEl0IGxvb2tzIGxpa2UgdGhlIEJBUiBj
b250YWluaW5nIHRoZSBicmlkZ2Ugd2luZG93IGlzIG5vdCBiZWluZyBhc3NpZ25lZCwNCj4gc28g
bm8gZGV2aWNlcyBvbiBidXMgMSBhcmUgZGlzY292ZXJlZC4NCg0KQ2FuIHlvdSBjb25maXJtIHRo
ZSBkdHNpIHlvdSBhcmUgdXNpbmcuLi4iaW14NnFkbC5kdHNpIiA/DQoNClRoYW5rcw0KDQpHYWIN
Cg0KPiANCj4gSSB3aWxsIHNlbmQgdGhlIGZ1bGwgdjIgYW5kIHYzIGRtZXNnIG91dHB1dCBzZXBh
cmF0ZWx5Lg0KPiANCj4gDQo+IFRoYW5rcywNCj4gDQo+IEphbWVzDQo+IA0KPiAtLQ0KPiBUbyB1
bnN1YnNjcmliZSBmcm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJzY3JpYmUgbGlu
dXgtcGNpIiBpbg0KPiB0aGUgYm9keSBvZiBhIG1lc3NhZ2UgdG8gbWFqb3Jkb21vQHZnZXIua2Vy
bmVsLm9yZw0KPiBNb3JlIG1ham9yZG9tbyBpbmZvIGF0ICBodHRwOi8vdmdlci5rZXJuZWwub3Jn
L21ham9yZG9tby1pbmZvLmh0bWwNCg==

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[James Morse]

On 02/07/15 08:24, Gabriele Paoloni wrote:
>> It looks like the BAR containing the bridge window is not being assigned,
>> so no devices on bus 1 are discovered.
> 
> Can you confirm the dtsi you are using..."imx6qdl.dtsi" ?

Yes, that looks right.

The on-disk file was 'imx6q-sabrelite.dtb' when I received the board, I
replaced it with the one from the v4.1 kernel tree.

Decompiled from /sys/firmware/fdt (to eliminate bootloader trickery), the
pcie section reads:
pcie@0x01000000 {
	compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
	reg = <0x1ffc000 0x4000 0x1f00000 0x80000>;
	reg-names = "dbi", "config";
	#address-cells = <0x3>;
	#size-cells = <0x2>;
	device_type = "pci";
	ranges = <0x800 0x0 0x1f00000 0x1f00000 0x0 0x80000 0x81000000 0x0 0x0
0x1f80000 0x0 0x10000 0x82000000 0x0 0x1000000 0x1000000 0x0 0xf00000>;
	num-lanes = <0x1>;
	interrupts = <0x0 0x78 0x4>;
	interrupt-names = "msi";
	#interrupt-cells = <0x1>;
	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
	interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x7b 0x4 0x0 0x0 0x0 0x2 0x1 0x0
0x7a 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x79 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x78 0x4>;
	clocks = <0x3 0x90 0x3 0xce 0x3 0xbd>;
	clock-names = "pcie", "pcie_bus", "pcie_phy";
	status = "okay";
};



James

Re: [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Liviu Dudau]

On Wed, Jul 01, 2015 at 10:43:33AM +0100, Zhou Wang wrote:
> This patch had added by Arnd Bergmann during last reviewing of v1 patchset[1].
> 
> PCI core codes call pcibios_align_resource(). In ARM specific one, it will
> dereference pci_sys_data and call sys->align_resource. If we try to unify ARM
> and ARM64 PCIe API in pcie-designware. it will bring kernel crash when run into
> this dereferencing.
> 
> However, in ARM there is only pci-mvebu which implements align_resource. So
> add align_resource call back in pci_host_bridge structure and override
> pcibios_align_resource with it.
> 
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> 
> [1] http://www.spinics.net/lists/linux-pci/msg41671.html
> ---
>  arch/arm/kernel/bios32.c     |  6 ------
>  drivers/pci/host/pci-mvebu.c | 47 ++++++++++++++++++++++++++++----------------
>  drivers/pci/setup-res.c      | 27 ++++++++++++++++++++-----
>  include/linux/pci.h          |  3 +++
>  4 files changed, 55 insertions(+), 28 deletions(-)
> 
> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> index fcbbbb1..b01189f 100644
> --- a/arch/arm/kernel/bios32.c
> +++ b/arch/arm/kernel/bios32.c
> @@ -468,7 +468,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
>  		sys->busnr   = busnr;
>  		sys->swizzle = hw->swizzle;
>  		sys->map_irq = hw->map_irq;
> -		sys->align_resource = hw->align_resource;
>  		INIT_LIST_HEAD(&sys->resources);
>  
>  		if (hw->private_data)
> @@ -588,8 +587,6 @@ char * __init pcibios_setup(char *str)
>  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  				resource_size_t size, resource_size_t align)
>  {
> -	struct pci_dev *dev = data;
> -	struct pci_sys_data *sys = dev->sysdata;
>  	resource_size_t start = res->start;
>  
>  	if (res->flags & IORESOURCE_IO && start & 0x300)
> @@ -597,9 +594,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  
>  	start = (start + align - 1) & ~(align - 1);
>  
> -	if (sys->align_resource)
> -		return sys->align_resource(dev, res, start, size, align);
> -
>  	return start;
>  }
>  
> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> index 1ab8635..155d05f 100644
> --- a/drivers/pci/host/pci-mvebu.c
> +++ b/drivers/pci/host/pci-mvebu.c
> @@ -22,6 +22,8 @@
>  #include <linux/of_pci.h>
>  #include <linux/of_platform.h>
>  
> +#include "../pci.h" /* HACK to see pci_find_host_bridge */
> +
>  /*
>   * PCIe unit register offsets.
>   */
> @@ -751,27 +753,20 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
>  	return 1;
>  }
>  
> -static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> +static resource_size_t mvebu_pcie_align_resource(void *data,
> +						 const struct resource *res,
> +						 resource_size_t size,
> +						 resource_size_t align)
>  {
> -	struct mvebu_pcie *pcie = sys_to_pcie(sys);
> -	struct pci_bus *bus;
> +	struct pci_dev *dev = data;
>  
> -	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
> -				  &mvebu_pcie_ops, sys, &sys->resources);
> -	if (!bus)
> -		return NULL;
> +	resource_size_t start = res->start;
>  
> -	pci_scan_child_bus(bus);
> +	if (res->flags & IORESOURCE_IO && start & 0x300)
> +		start = (start + 0x3ff) & ~0x3ff;
>  
> -	return bus;
> -}
> +	start = (start + align - 1) & ~(align - 1);

Honestly, I don't see here anything that is mvebu specific. Could you move
this function in the generic pci/host area and have a flag in the pci_host_bridge
structure whether the function should be called or not? I know that in a way
that looks very close to the existing implementation which uses pcibios_align_resource,
but the problem with pcibios_ version is that it is arch specific and not driver
specific the way we want.

Having this version as a generic implementation would also remove at least 2 more
arch version, possibly more after testing by the arch maintainers.

Best regards,
Liviu

>  
> -static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
> -						 const struct resource *res,
> -						 resource_size_t start,
> -						 resource_size_t size,
> -						 resource_size_t align)
> -{
>  	if (dev->bus->number != 0)
>  		return start;
>  
> @@ -796,6 +791,25 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
>  		return start;
>  }
>  
> +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> +{
> +	struct mvebu_pcie *pcie = sys_to_pcie(sys);
> +	struct pci_host_bridge *phb;
> +	struct pci_bus *bus;
> +
> +	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
> +				  &mvebu_pcie_ops, sys, &sys->resources);
> +	if (!bus)
> +		return NULL;
> +
> +	phb = pci_find_host_bridge(bus);
> +	phb->align_resource = mvebu_pcie_align_resource;
> +
> +	pci_scan_child_bus(bus);
> +
> +	return bus;
> +}
> +
>  static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
>  {
>  	struct hw_pci hw;
> @@ -812,7 +826,6 @@ static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
>  	hw.scan           = mvebu_pcie_scan_bus;
>  	hw.map_irq        = of_irq_parse_and_map_pci;
>  	hw.ops            = &mvebu_pcie_ops;
> -	hw.align_resource = mvebu_pcie_align_resource;
>  
>  	pci_common_init(&hw);
>  }
> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> index 232f925..73abca7 100644
> --- a/drivers/pci/setup-res.c
> +++ b/drivers/pci/setup-res.c
> @@ -200,7 +200,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
>  }
>  
>  static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
> -		int resno, resource_size_t size, resource_size_t align)
> +		int resno, resource_size_t size, resource_size_t align,
> +		resource_size_t (*alignf)(void *,
> +					  const struct resource *,
> +					  resource_size_t,
> +					  resource_size_t))
>  {
>  	struct resource *res = dev->resource + resno;
>  	resource_size_t min;
> @@ -217,7 +221,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>  	 */
>  	ret = pci_bus_alloc_resource(bus, res, size, align, min,
>  				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
> -				     pcibios_align_resource, dev);
> +				     alignf, dev);
>  	if (ret == 0)
>  		return 0;
>  
> @@ -229,7 +233,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>  	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
>  		ret = pci_bus_alloc_resource(bus, res, size, align, min,
>  					     IORESOURCE_PREFETCH,
> -					     pcibios_align_resource, dev);
> +					     alignf, dev);
>  		if (ret == 0)
>  			return 0;
>  	}
> @@ -242,7 +246,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>  	 */
>  	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
>  		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
> -					     pcibios_align_resource, dev);
> +					     alignf, dev);
>  
>  	return ret;
>  }
> @@ -251,10 +255,23 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno,
>  				resource_size_t size, resource_size_t min_align)
>  {
>  	struct pci_bus *bus;
> +	struct pci_host_bridge *phb;
> +	resource_size_t (*alignf)(void *,
> +				  const struct resource *,
> +				  resource_size_t,
> +				  resource_size_t);
>  	int ret;
>  
>  	bus = dev->bus;
> -	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
> +	phb = pci_find_host_bridge(bus);
> +
> +	if (phb->align_resource)
> +		alignf = phb->align_resource;
> +	else
> +		alignf = pcibios_align_resource;
> +
> +	while ((ret = __pci_assign_resource(bus, dev, resno, size,
> +					    min_align, alignf))) {
>  		if (!bus->parent || !bus->self->transparent)
>  			break;
>  		bus = bus->parent;
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 353db8d..39e48fc 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -404,6 +404,9 @@ struct pci_host_bridge {
>  	struct device dev;
>  	struct pci_bus *bus;		/* root bus */
>  	struct list_head windows;	/* resource_entry */
> +	resource_size_t (*align_resource)(void *data,
> +			 const struct resource *res,
> +			 resource_size_t size, resource_size_t align);
>  	void (*release_fn)(struct pci_host_bridge *);
>  	void *release_data;
>  	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */
> -- 
> 1.9.1
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Zhou Wang]

On 2015/7/1 22:26, James Morse wrote:
> Zhou Wang wrote:
>> I tested this patch on D02 board of Hisilicon. It works well.
>> I have compiled the driver with multi_v7_defconfig. However, I don't
>> have
>> ARM32 PCIe related board to do test. It will be appreciated if someone
>> could
>> help to test it.
>>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
>> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>> Tested-by: James Morse <james.morse@arm.com>
> 
> Tests on this new series, using the same i.MX 6Quad board, are not working.
> 
> The network card is no longer detected, and I get a lockup when removing
> the root bridge and rescanning.
> 
> Partial dmesg output below. Significantly, the lines:
>> [    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
>> [    0.152142]   No bus range found for /soc/pcie@0x01000000, using [bus
> 00-ff]
> are new.
> 
> Both series are applied to v4.1, use the same .config file, and the same dtb.
> I will investigate further.
> 
> (Re-testing v2 works, so this isn't an interim hardware failure)
> 
> Thanks,
> 
> James
>

Hi James,

There are something wrong with v3 patch.

pp->io_mod_base = of_read_number(parser_range_end -
		of_n_addr_cells(np) - 5 + na, ns);
pp->mem_mod_base = of_read_number(parser_range_end -
		of_n_addr_cells(np) - 5 + na, ns);
pp->cfg0_mod_base = of_read_number(parser_range_end -
		of_n_addr_cells(np) - 5 + na, ns);
are wrong.

The ranges item in your dts is:
ranges = <0x800 0x0 0x1f00000 0x1f00000 0x0 0x80000
	  0x81000000 0x0 0x0  0x1f80000 0x0 0x10000
	  0x82000000 0x0 0x1000000 0x1000000 0x0 0xf00000>;
parser_range_end points to the end of ranges(0xf00000) directly. In v2 patch,
of_read_number is of_read_number(parser.range - parser.np + na, ns); parser.range
points to the end of each line in ranges item.

When I did test on D02 board with intel82599 card, I set ranges item as:
ranges = <0x03000000 0 0xb0000000 0x220 0x00000000 0 0xf000000>;
It is just one line. In this case, parser_range_end is same with parser.range.
That is why it happened to work well on D02 board.

very sorry to bother you about this problem.

Thanks,
Zhou

> 
> 
> root@localhost:~# dmesg | grep -i pci
> [    0.126184] PCI: CLS 0 bytes, default 64
> [    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
> [    0.152142]   No bus range found for /soc/pcie@0x01000000, using [bus 00-ff]
> [    0.154183] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus 0000:00
> [    0.154201] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    0.154215] pci_bus 0000:00: root bus resource [???
> 0x01f00000-0x01f7ffff flags 0x0]
> [    0.154228] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
> [    0.154270] pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
> [    0.154306] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
> [    0.154333] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
> [    0.154352] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
> [    0.154377] pci 0000:00:00.0: IOMMU is currently not supported for PCI
> [    0.154429] pci 0000:00:00.0: supports D1
> [    0.154440] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
> [    0.154683] PCI: bus0: Fast back to back transfers disabled
> [    0.154806] PCI: bus1: Fast back to back transfers enabled
> [    0.154884] pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
> [    0.154903] pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-0x0110ffff
> pref]
> [    0.154917] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    0.155145] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
> [    0.155161] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
> [    0.155279] aer 0000:00:00.0:pcie02: service driver aer loaded
> [    1.188840] ehci-pci: EHCI PCI platform driver
> [    1.232518] ohci-pci: OHCI PCI platform driver
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> .
> 

Re: [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Zhou Wang]

On 2015/7/3 1:50, Liviu Dudau wrote:
> On Wed, Jul 01, 2015 at 10:43:33AM +0100, Zhou Wang wrote:
>> This patch had added by Arnd Bergmann during last reviewing of v1 patchset[1].
>>
>> PCI core codes call pcibios_align_resource(). In ARM specific one, it will
>> dereference pci_sys_data and call sys->align_resource. If we try to unify ARM
>> and ARM64 PCIe API in pcie-designware. it will bring kernel crash when run into
>> this dereferencing.
>>
>> However, in ARM there is only pci-mvebu which implements align_resource. So
>> add align_resource call back in pci_host_bridge structure and override
>> pcibios_align_resource with it.
>>
>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>>
>> [1] http://www.spinics.net/lists/linux-pci/msg41671.html
>> ---
>>  arch/arm/kernel/bios32.c     |  6 ------
>>  drivers/pci/host/pci-mvebu.c | 47 ++++++++++++++++++++++++++++----------------
>>  drivers/pci/setup-res.c      | 27 ++++++++++++++++++++-----
>>  include/linux/pci.h          |  3 +++
>>  4 files changed, 55 insertions(+), 28 deletions(-)
>>
>> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
>> index fcbbbb1..b01189f 100644
>> --- a/arch/arm/kernel/bios32.c
>> +++ b/arch/arm/kernel/bios32.c
>> @@ -468,7 +468,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
>>  		sys->busnr   = busnr;
>>  		sys->swizzle = hw->swizzle;
>>  		sys->map_irq = hw->map_irq;
>> -		sys->align_resource = hw->align_resource;
>>  		INIT_LIST_HEAD(&sys->resources);
>>  
>>  		if (hw->private_data)
>> @@ -588,8 +587,6 @@ char * __init pcibios_setup(char *str)
>>  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>>  				resource_size_t size, resource_size_t align)
>>  {
>> -	struct pci_dev *dev = data;
>> -	struct pci_sys_data *sys = dev->sysdata;
>>  	resource_size_t start = res->start;
>>  
>>  	if (res->flags & IORESOURCE_IO && start & 0x300)
>> @@ -597,9 +594,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>>  
>>  	start = (start + align - 1) & ~(align - 1);
>>  
>> -	if (sys->align_resource)
>> -		return sys->align_resource(dev, res, start, size, align);
>> -
>>  	return start;
>>  }
>>  
>> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
>> index 1ab8635..155d05f 100644
>> --- a/drivers/pci/host/pci-mvebu.c
>> +++ b/drivers/pci/host/pci-mvebu.c
>> @@ -22,6 +22,8 @@
>>  #include <linux/of_pci.h>
>>  #include <linux/of_platform.h>
>>  
>> +#include "../pci.h" /* HACK to see pci_find_host_bridge */
>> +
>>  /*
>>   * PCIe unit register offsets.
>>   */
>> @@ -751,27 +753,20 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
>>  	return 1;
>>  }
>>  
>> -static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>> +static resource_size_t mvebu_pcie_align_resource(void *data,
>> +						 const struct resource *res,
>> +						 resource_size_t size,
>> +						 resource_size_t align)
>>  {
>> -	struct mvebu_pcie *pcie = sys_to_pcie(sys);
>> -	struct pci_bus *bus;
>> +	struct pci_dev *dev = data;
>>  
>> -	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
>> -				  &mvebu_pcie_ops, sys, &sys->resources);
>> -	if (!bus)
>> -		return NULL;
>> +	resource_size_t start = res->start;
>>  
>> -	pci_scan_child_bus(bus);
>> +	if (res->flags & IORESOURCE_IO && start & 0x300)
>> +		start = (start + 0x3ff) & ~0x3ff;
>>  
>> -	return bus;
>> -}
>> +	start = (start + align - 1) & ~(align - 1);
> 
> Honestly, I don't see here anything that is mvebu specific. Could you move

What I mean is that there is only mvebu who implemented sys->align_resource callback in ARM
arch.

> this function in the generic pci/host area and have a flag in the pci_host_bridge
> structure whether the function should be called or not? I know that in a way
> that looks very close to the existing implementation which uses pcibios_align_resource,

I am confused about "the existing implementation". Now pcibios_align_resource are
implemented by each arch code and are called directly. Did I miss anything about
pcibios_align_resource?

Best rgards,
Zhou

> but the problem with pcibios_ version is that it is arch specific and not driver
> specific the way we want.
> 
> Having this version as a generic implementation would also remove at least 2 more
> arch version, possibly more after testing by the arch maintainers.
> 
> Best regards,
> Liviu
> 
>>  
>> -static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
>> -						 const struct resource *res,
>> -						 resource_size_t start,
>> -						 resource_size_t size,
>> -						 resource_size_t align)
>> -{
>>  	if (dev->bus->number != 0)
>>  		return start;
>>  
>> @@ -796,6 +791,25 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
>>  		return start;
>>  }
>>  
>> +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>> +{
>> +	struct mvebu_pcie *pcie = sys_to_pcie(sys);
>> +	struct pci_host_bridge *phb;
>> +	struct pci_bus *bus;
>> +
>> +	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
>> +				  &mvebu_pcie_ops, sys, &sys->resources);
>> +	if (!bus)
>> +		return NULL;
>> +
>> +	phb = pci_find_host_bridge(bus);
>> +	phb->align_resource = mvebu_pcie_align_resource;
>> +
>> +	pci_scan_child_bus(bus);
>> +
>> +	return bus;
>> +}
>> +
>>  static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
>>  {
>>  	struct hw_pci hw;
>> @@ -812,7 +826,6 @@ static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
>>  	hw.scan           = mvebu_pcie_scan_bus;
>>  	hw.map_irq        = of_irq_parse_and_map_pci;
>>  	hw.ops            = &mvebu_pcie_ops;
>> -	hw.align_resource = mvebu_pcie_align_resource;
>>  
>>  	pci_common_init(&hw);
>>  }
>> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
>> index 232f925..73abca7 100644
>> --- a/drivers/pci/setup-res.c
>> +++ b/drivers/pci/setup-res.c
>> @@ -200,7 +200,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
>>  }
>>  
>>  static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>> -		int resno, resource_size_t size, resource_size_t align)
>> +		int resno, resource_size_t size, resource_size_t align,
>> +		resource_size_t (*alignf)(void *,
>> +					  const struct resource *,
>> +					  resource_size_t,
>> +					  resource_size_t))
>>  {
>>  	struct resource *res = dev->resource + resno;
>>  	resource_size_t min;
>> @@ -217,7 +221,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>>  	 */
>>  	ret = pci_bus_alloc_resource(bus, res, size, align, min,
>>  				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
>> -				     pcibios_align_resource, dev);
>> +				     alignf, dev);
>>  	if (ret == 0)
>>  		return 0;
>>  
>> @@ -229,7 +233,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>>  	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
>>  		ret = pci_bus_alloc_resource(bus, res, size, align, min,
>>  					     IORESOURCE_PREFETCH,
>> -					     pcibios_align_resource, dev);
>> +					     alignf, dev);
>>  		if (ret == 0)
>>  			return 0;
>>  	}
>> @@ -242,7 +246,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
>>  	 */
>>  	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
>>  		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
>> -					     pcibios_align_resource, dev);
>> +					     alignf, dev);
>>  
>>  	return ret;
>>  }
>> @@ -251,10 +255,23 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno,
>>  				resource_size_t size, resource_size_t min_align)
>>  {
>>  	struct pci_bus *bus;
>> +	struct pci_host_bridge *phb;
>> +	resource_size_t (*alignf)(void *,
>> +				  const struct resource *,
>> +				  resource_size_t,
>> +				  resource_size_t);
>>  	int ret;
>>  
>>  	bus = dev->bus;
>> -	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
>> +	phb = pci_find_host_bridge(bus);
>> +
>> +	if (phb->align_resource)
>> +		alignf = phb->align_resource;
>> +	else
>> +		alignf = pcibios_align_resource;
>> +
>> +	while ((ret = __pci_assign_resource(bus, dev, resno, size,
>> +					    min_align, alignf))) {
>>  		if (!bus->parent || !bus->self->transparent)
>>  			break;
>>  		bus = bus->parent;
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 353db8d..39e48fc 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -404,6 +404,9 @@ struct pci_host_bridge {
>>  	struct device dev;
>>  	struct pci_bus *bus;		/* root bus */
>>  	struct list_head windows;	/* resource_entry */
>> +	resource_size_t (*align_resource)(void *data,
>> +			 const struct resource *res,
>> +			 resource_size_t size, resource_size_t align);
>>  	void (*release_fn)(struct pci_host_bridge *);
>>  	void *release_data;
>>  	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */
>> -- 
>> 1.9.1
>>
> 

Re: [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Liviu Dudau]

On Tue, Jul 07, 2015 at 06:44:01AM +0100, Zhou Wang wrote:
> On 2015/7/3 1:50, Liviu Dudau wrote:
> > On Wed, Jul 01, 2015 at 10:43:33AM +0100, Zhou Wang wrote:
> >> This patch had added by Arnd Bergmann during last reviewing of v1 patchset[1].
> >>
> >> PCI core codes call pcibios_align_resource(). In ARM specific one, it will
> >> dereference pci_sys_data and call sys->align_resource. If we try to unify ARM
> >> and ARM64 PCIe API in pcie-designware. it will bring kernel crash when run into
> >> this dereferencing.
> >>
> >> However, in ARM there is only pci-mvebu which implements align_resource. So
> >> add align_resource call back in pci_host_bridge structure and override
> >> pcibios_align_resource with it.
> >>
> >> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> >> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> >> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> >>
> >> [1] http://www.spinics.net/lists/linux-pci/msg41671.html
> >> ---
> >>  arch/arm/kernel/bios32.c     |  6 ------
> >>  drivers/pci/host/pci-mvebu.c | 47 ++++++++++++++++++++++++++++----------------
> >>  drivers/pci/setup-res.c      | 27 ++++++++++++++++++++-----
> >>  include/linux/pci.h          |  3 +++
> >>  4 files changed, 55 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> >> index fcbbbb1..b01189f 100644
> >> --- a/arch/arm/kernel/bios32.c
> >> +++ b/arch/arm/kernel/bios32.c
> >> @@ -468,7 +468,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
> >>  		sys->busnr   = busnr;
> >>  		sys->swizzle = hw->swizzle;
> >>  		sys->map_irq = hw->map_irq;
> >> -		sys->align_resource = hw->align_resource;
> >>  		INIT_LIST_HEAD(&sys->resources);
> >>  
> >>  		if (hw->private_data)
> >> @@ -588,8 +587,6 @@ char * __init pcibios_setup(char *str)
> >>  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
> >>  				resource_size_t size, resource_size_t align)
> >>  {
> >> -	struct pci_dev *dev = data;
> >> -	struct pci_sys_data *sys = dev->sysdata;
> >>  	resource_size_t start = res->start;
> >>  
> >>  	if (res->flags & IORESOURCE_IO && start & 0x300)
> >> @@ -597,9 +594,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
> >>  
> >>  	start = (start + align - 1) & ~(align - 1);
> >>  
> >> -	if (sys->align_resource)
> >> -		return sys->align_resource(dev, res, start, size, align);
> >> -
> >>  	return start;
> >>  }
> >>  
> >> diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
> >> index 1ab8635..155d05f 100644
> >> --- a/drivers/pci/host/pci-mvebu.c
> >> +++ b/drivers/pci/host/pci-mvebu.c
> >> @@ -22,6 +22,8 @@
> >>  #include <linux/of_pci.h>
> >>  #include <linux/of_platform.h>
> >>  
> >> +#include "../pci.h" /* HACK to see pci_find_host_bridge */
> >> +
> >>  /*
> >>   * PCIe unit register offsets.
> >>   */
> >> @@ -751,27 +753,20 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
> >>  	return 1;
> >>  }
> >>  
> >> -static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> >> +static resource_size_t mvebu_pcie_align_resource(void *data,
> >> +						 const struct resource *res,
> >> +						 resource_size_t size,
> >> +						 resource_size_t align)
> >>  {
> >> -	struct mvebu_pcie *pcie = sys_to_pcie(sys);
> >> -	struct pci_bus *bus;
> >> +	struct pci_dev *dev = data;
> >>  
> >> -	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
> >> -				  &mvebu_pcie_ops, sys, &sys->resources);
> >> -	if (!bus)
> >> -		return NULL;
> >> +	resource_size_t start = res->start;
> >>  
> >> -	pci_scan_child_bus(bus);
> >> +	if (res->flags & IORESOURCE_IO && start & 0x300)
> >> +		start = (start + 0x3ff) & ~0x3ff;
> >>  
> >> -	return bus;
> >> -}
> >> +	start = (start + align - 1) & ~(align - 1);
> > 
> > Honestly, I don't see here anything that is mvebu specific. Could you move
> 
> What I mean is that there is only mvebu who implemented sys->align_resource callback in ARM
> arch.
> 
> > this function in the generic pci/host area and have a flag in the pci_host_bridge
> > structure whether the function should be called or not? I know that in a way
> > that looks very close to the existing implementation which uses pcibios_align_resource,
> 
> I am confused about "the existing implementation". Now pcibios_align_resource are
> implemented by each arch code and are called directly. Did I miss anything about
> pcibios_align_resource?

Sorry, I meant existing implementation_s_ and yes, I was reffering to the arch specific
code. If you look at the cris, frv/mb93090-mb00, m68k, microblaze, powerpc, unicore32
and x86 they all share the code with your version, plus or minus additional checks.
I was thinking that for those arch versions that match your version you can create just
one version and use it as the alignf function.

Best regards,
Liviu

> 
> Best rgards,
> Zhou
> 
> > but the problem with pcibios_ version is that it is arch specific and not driver
> > specific the way we want.
> > 
> > Having this version as a generic implementation would also remove at least 2 more
> > arch version, possibly more after testing by the arch maintainers.
> > 
> > Best regards,
> > Liviu
> > 
> >>  
> >> -static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
> >> -						 const struct resource *res,
> >> -						 resource_size_t start,
> >> -						 resource_size_t size,
> >> -						 resource_size_t align)
> >> -{
> >>  	if (dev->bus->number != 0)
> >>  		return start;
> >>  
> >> @@ -796,6 +791,25 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
> >>  		return start;
> >>  }
> >>  
> >> +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> >> +{
> >> +	struct mvebu_pcie *pcie = sys_to_pcie(sys);
> >> +	struct pci_host_bridge *phb;
> >> +	struct pci_bus *bus;
> >> +
> >> +	bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
> >> +				  &mvebu_pcie_ops, sys, &sys->resources);
> >> +	if (!bus)
> >> +		return NULL;
> >> +
> >> +	phb = pci_find_host_bridge(bus);
> >> +	phb->align_resource = mvebu_pcie_align_resource;
> >> +
> >> +	pci_scan_child_bus(bus);
> >> +
> >> +	return bus;
> >> +}
> >> +
> >>  static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
> >>  {
> >>  	struct hw_pci hw;
> >> @@ -812,7 +826,6 @@ static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
> >>  	hw.scan           = mvebu_pcie_scan_bus;
> >>  	hw.map_irq        = of_irq_parse_and_map_pci;
> >>  	hw.ops            = &mvebu_pcie_ops;
> >> -	hw.align_resource = mvebu_pcie_align_resource;
> >>  
> >>  	pci_common_init(&hw);
> >>  }
> >> diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
> >> index 232f925..73abca7 100644
> >> --- a/drivers/pci/setup-res.c
> >> +++ b/drivers/pci/setup-res.c
> >> @@ -200,7 +200,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
> >>  }
> >>  
> >>  static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
> >> -		int resno, resource_size_t size, resource_size_t align)
> >> +		int resno, resource_size_t size, resource_size_t align,
> >> +		resource_size_t (*alignf)(void *,
> >> +					  const struct resource *,
> >> +					  resource_size_t,
> >> +					  resource_size_t))
> >>  {
> >>  	struct resource *res = dev->resource + resno;
> >>  	resource_size_t min;
> >> @@ -217,7 +221,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
> >>  	 */
> >>  	ret = pci_bus_alloc_resource(bus, res, size, align, min,
> >>  				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
> >> -				     pcibios_align_resource, dev);
> >> +				     alignf, dev);
> >>  	if (ret == 0)
> >>  		return 0;
> >>  
> >> @@ -229,7 +233,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
> >>  	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
> >>  		ret = pci_bus_alloc_resource(bus, res, size, align, min,
> >>  					     IORESOURCE_PREFETCH,
> >> -					     pcibios_align_resource, dev);
> >> +					     alignf, dev);
> >>  		if (ret == 0)
> >>  			return 0;
> >>  	}
> >> @@ -242,7 +246,7 @@ static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
> >>  	 */
> >>  	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
> >>  		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
> >> -					     pcibios_align_resource, dev);
> >> +					     alignf, dev);
> >>  
> >>  	return ret;
> >>  }
> >> @@ -251,10 +255,23 @@ static int _pci_assign_resource(struct pci_dev *dev, int resno,
> >>  				resource_size_t size, resource_size_t min_align)
> >>  {
> >>  	struct pci_bus *bus;
> >> +	struct pci_host_bridge *phb;
> >> +	resource_size_t (*alignf)(void *,
> >> +				  const struct resource *,
> >> +				  resource_size_t,
> >> +				  resource_size_t);
> >>  	int ret;
> >>  
> >>  	bus = dev->bus;
> >> -	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
> >> +	phb = pci_find_host_bridge(bus);
> >> +
> >> +	if (phb->align_resource)
> >> +		alignf = phb->align_resource;
> >> +	else
> >> +		alignf = pcibios_align_resource;
> >> +
> >> +	while ((ret = __pci_assign_resource(bus, dev, resno, size,
> >> +					    min_align, alignf))) {
> >>  		if (!bus->parent || !bus->self->transparent)
> >>  			break;
> >>  		bus = bus->parent;
> >> diff --git a/include/linux/pci.h b/include/linux/pci.h
> >> index 353db8d..39e48fc 100644
> >> --- a/include/linux/pci.h
> >> +++ b/include/linux/pci.h
> >> @@ -404,6 +404,9 @@ struct pci_host_bridge {
> >>  	struct device dev;
> >>  	struct pci_bus *bus;		/* root bus */
> >>  	struct list_head windows;	/* resource_entry */
> >> +	resource_size_t (*align_resource)(void *data,
> >> +			 const struct resource *res,
> >> +			 resource_size_t size, resource_size_t align);
> >>  	void (*release_fn)(struct pci_host_bridge *);
> >>  	void *release_data;
> >>  	unsigned int ignore_reset_delay:1;	/* for entire hierarchy */
> >> -- 
> >> 1.9.1
> >>
> > 
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

RE: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Gabriele Paoloni]

SSBoYXZlIGp1c3Qgc2VudCB0aGlzIHBhdGNoICJbUEFUQ0hdIFN0b3JlIFBDSWUgY29udHJvbGxl
cnMgYWRkcmVzcyBpbiBzdHJ1Y3Qgb2ZfcGNpX3JhbmdlIi4NCg0KSXQgd291bGQgYmUgbmVlZGVk
IGJ5ICJwY2llX2Rlc2lnbndhcmUuYyIgdG8gcmV0cmlldmUgdGhlIFBDSSBjb250cm9sbGVyIGFk
ZHJlc3NlcyBmcm9tICJ3aW4tPl9fcmVzLnN0YXJ0Ii4NCg0KU28gd2UgZG8gbm90IG5lZWQgdG8g
cmV0cmlldmUgaW5mbyBmcm9tIHRoZSBEVCBwYXJzZXIgYW55bW9yZSBhbmQgd2UgY2FuIHVzZSB0
aGUgbmV3IFBDSSBEVCBwYXJzaW5nIEFQSQ0KDQpUaGlzIHByb2JsZW0gd2FzIGFscmVhZHkgZGlz
Y3Vzc2VkIGluIHRoaXMgdGhyZWFkOg0KaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvcGlwZXJt
YWlsL2xpbnV4LWFybS1rZXJuZWwvMjAxNS1KYW51YXJ5LzMxNzc0My5odG1sDQoNCg0KPiAtLS0t
LU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBXYW5nemhvdSAoQikNCj4gU2VudDogVHVl
c2RheSwgSnVseSAwNywgMjAxNSA0OjQ0IEFNDQo+IFRvOiBKYW1lcyBNb3JzZQ0KPiBDYzogR2Fi
cmllbGUgUGFvbG9uaTsgQmpvcm4gSGVsZ2FhczsgSmluZ29vIEhhbjsgUHJhdHl1c2ggQW5hbmQ7
IEFybmQNCj4gQmVyZ21hbm47IExpdml1IER1ZGF1OyBraXNob25AdGkuY29tOyB4b2JzQGtvc2Fn
aS5jb207IG0tDQo+IGthcmljaGVyaTJAdGkuY29tOyBNaW5naHVhbi5MaWFuQGZyZWVzY2FsZS5j
b207IGxpbnV4LQ0KPiBwY2lAdmdlci5rZXJuZWwub3JnOyBsaW51eC1hcm0ta2VybmVsQGxpc3Rz
LmluZnJhZGVhZC5vcmc7DQo+IGRldmljZXRyZWVAdmdlci5rZXJuZWwub3JnOyBZdWFuemhpY2hh
bmc7IFpodWRhY2FpOyB6aGFuZ2p1a3VvOw0KPiBxaXV6aGVuZmE7IExpZ3Vvemh1IChLZW5uZXRo
KQ0KPiBTdWJqZWN0OiBSZTogW1BBVENIIHYzIDIvNV0gUENJOiBkZXNpZ253YXJlOiBBZGQgQVJN
NjQgc3VwcG9ydA0KPiANCj4gT24gMjAxNS83LzEgMjI6MjYsIEphbWVzIE1vcnNlIHdyb3RlOg0K
PiA+IFpob3UgV2FuZyB3cm90ZToNCj4gPj4gSSB0ZXN0ZWQgdGhpcyBwYXRjaCBvbiBEMDIgYm9h
cmQgb2YgSGlzaWxpY29uLiBJdCB3b3JrcyB3ZWxsLg0KPiA+PiBJIGhhdmUgY29tcGlsZWQgdGhl
IGRyaXZlciB3aXRoIG11bHRpX3Y3X2RlZmNvbmZpZy4gSG93ZXZlciwgSSBkb24ndA0KPiA+PiBo
YXZlDQo+ID4+IEFSTTMyIFBDSWUgcmVsYXRlZCBib2FyZCB0byBkbyB0ZXN0LiBJdCB3aWxsIGJl
IGFwcHJlY2lhdGVkIGlmDQo+IHNvbWVvbmUNCj4gPj4gY291bGQNCj4gPj4gaGVscCB0byB0ZXN0
IGl0Lg0KPiA+Pg0KPiA+PiBTaWduZWQtb2ZmLWJ5OiBaaG91IFdhbmcgPHdhbmd6aG91MUBoaXNp
bGljb24uY29tPg0KPiA+PiBTaWduZWQtb2ZmLWJ5OiBBcm5kIEJlcmdtYW5uIDxhcm5kQGFybmRi
LmRlPg0KPiA+PiBTaWduZWQtb2ZmLWJ5OiBHYWJyaWVsZSBQYW9sb25pIDxnYWJyaWVsZS5wYW9s
b25pQGh1YXdlaS5jb20+DQo+ID4+IFRlc3RlZC1ieTogRmFicmljZSBHYXNuaWVyIDxmYWJyaWNl
Lmdhc25pZXJAc3QuY29tPg0KPiA+PiBUZXN0ZWQtYnk6IEphbWVzIE1vcnNlIDxqYW1lcy5tb3Jz
ZUBhcm0uY29tPg0KPiA+DQo+ID4gVGVzdHMgb24gdGhpcyBuZXcgc2VyaWVzLCB1c2luZyB0aGUg
c2FtZSBpLk1YIDZRdWFkIGJvYXJkLCBhcmUgbm90DQo+IHdvcmtpbmcuDQo+ID4NCj4gPiBUaGUg
bmV0d29yayBjYXJkIGlzIG5vIGxvbmdlciBkZXRlY3RlZCwgYW5kIEkgZ2V0IGEgbG9ja3VwIHdo
ZW4NCj4gcmVtb3ZpbmcNCj4gPiB0aGUgcm9vdCBicmlkZ2UgYW5kIHJlc2Nhbm5pbmcuDQo+ID4N
Cj4gPiBQYXJ0aWFsIGRtZXNnIG91dHB1dCBiZWxvdy4gU2lnbmlmaWNhbnRseSwgdGhlIGxpbmVz
Og0KPiA+PiBbICAgIDAuMTUyMTI4XSBQQ0kgaG9zdCBicmlkZ2UgL3NvYy9wY2llQDB4MDEwMDAw
MDAgcmFuZ2VzOg0KPiA+PiBbICAgIDAuMTUyMTQyXSAgIE5vIGJ1cyByYW5nZSBmb3VuZCBmb3Ig
L3NvYy9wY2llQDB4MDEwMDAwMDAsIHVzaW5nDQo+IFtidXMNCj4gPiAwMC1mZl0NCj4gPiBhcmUg
bmV3Lg0KPiA+DQo+ID4gQm90aCBzZXJpZXMgYXJlIGFwcGxpZWQgdG8gdjQuMSwgdXNlIHRoZSBz
YW1lIC5jb25maWcgZmlsZSwgYW5kIHRoZQ0KPiBzYW1lIGR0Yi4NCj4gPiBJIHdpbGwgaW52ZXN0
aWdhdGUgZnVydGhlci4NCj4gPg0KPiA+IChSZS10ZXN0aW5nIHYyIHdvcmtzLCBzbyB0aGlzIGlz
bid0IGFuIGludGVyaW0gaGFyZHdhcmUgZmFpbHVyZSkNCj4gPg0KPiA+IFRoYW5rcywNCj4gPg0K
PiA+IEphbWVzDQo+ID4NCj4gDQo+IEhpIEphbWVzLA0KPiANCj4gVGhlcmUgYXJlIHNvbWV0aGlu
ZyB3cm9uZyB3aXRoIHYzIHBhdGNoLg0KPiANCj4gcHAtPmlvX21vZF9iYXNlID0gb2ZfcmVhZF9u
dW1iZXIocGFyc2VyX3JhbmdlX2VuZCAtDQo+IAkJb2Zfbl9hZGRyX2NlbGxzKG5wKSAtIDUgKyBu
YSwgbnMpOw0KPiBwcC0+bWVtX21vZF9iYXNlID0gb2ZfcmVhZF9udW1iZXIocGFyc2VyX3Jhbmdl
X2VuZCAtDQo+IAkJb2Zfbl9hZGRyX2NlbGxzKG5wKSAtIDUgKyBuYSwgbnMpOw0KPiBwcC0+Y2Zn
MF9tb2RfYmFzZSA9IG9mX3JlYWRfbnVtYmVyKHBhcnNlcl9yYW5nZV9lbmQgLQ0KPiAJCW9mX25f
YWRkcl9jZWxscyhucCkgLSA1ICsgbmEsIG5zKTsNCj4gYXJlIHdyb25nLg0KPiANCj4gVGhlIHJh
bmdlcyBpdGVtIGluIHlvdXIgZHRzIGlzOg0KPiByYW5nZXMgPSA8MHg4MDAgMHgwIDB4MWYwMDAw
MCAweDFmMDAwMDAgMHgwIDB4ODAwMDANCj4gCSAgMHg4MTAwMDAwMCAweDAgMHgwICAweDFmODAw
MDAgMHgwIDB4MTAwMDANCj4gCSAgMHg4MjAwMDAwMCAweDAgMHgxMDAwMDAwIDB4MTAwMDAwMCAw
eDAgMHhmMDAwMDA+Ow0KPiBwYXJzZXJfcmFuZ2VfZW5kIHBvaW50cyB0byB0aGUgZW5kIG9mIHJh
bmdlcygweGYwMDAwMCkgZGlyZWN0bHkuIEluIHYyDQo+IHBhdGNoLA0KPiBvZl9yZWFkX251bWJl
ciBpcyBvZl9yZWFkX251bWJlcihwYXJzZXIucmFuZ2UgLSBwYXJzZXIubnAgKyBuYSwgbnMpOw0K
PiBwYXJzZXIucmFuZ2UNCj4gcG9pbnRzIHRvIHRoZSBlbmQgb2YgZWFjaCBsaW5lIGluIHJhbmdl
cyBpdGVtLg0KPiANCj4gV2hlbiBJIGRpZCB0ZXN0IG9uIEQwMiBib2FyZCB3aXRoIGludGVsODI1
OTkgY2FyZCwgSSBzZXQgcmFuZ2VzIGl0ZW0gYXM6DQo+IHJhbmdlcyA9IDwweDAzMDAwMDAwIDAg
MHhiMDAwMDAwMCAweDIyMCAweDAwMDAwMDAwIDAgMHhmMDAwMDAwPjsNCj4gSXQgaXMganVzdCBv
bmUgbGluZS4gSW4gdGhpcyBjYXNlLCBwYXJzZXJfcmFuZ2VfZW5kIGlzIHNhbWUgd2l0aA0KPiBw
YXJzZXIucmFuZ2UuDQo+IFRoYXQgaXMgd2h5IGl0IGhhcHBlbmVkIHRvIHdvcmsgd2VsbCBvbiBE
MDIgYm9hcmQuDQo+IA0KPiB2ZXJ5IHNvcnJ5IHRvIGJvdGhlciB5b3UgYWJvdXQgdGhpcyBwcm9i
bGVtLg0KPiANCj4gVGhhbmtzLA0KPiBaaG91DQo+IA0KPiA+DQo+ID4NCj4gPiByb290QGxvY2Fs
aG9zdDp+IyBkbWVzZyB8IGdyZXAgLWkgcGNpDQo+ID4gWyAgICAwLjEyNjE4NF0gUENJOiBDTFMg
MCBieXRlcywgZGVmYXVsdCA2NA0KPiA+IFsgICAgMC4xNTIxMjhdIFBDSSBob3N0IGJyaWRnZSAv
c29jL3BjaWVAMHgwMTAwMDAwMCByYW5nZXM6DQo+ID4gWyAgICAwLjE1MjE0Ml0gICBObyBidXMg
cmFuZ2UgZm91bmQgZm9yIC9zb2MvcGNpZUAweDAxMDAwMDAwLCB1c2luZw0KPiBbYnVzIDAwLWZm
XQ0KPiA+IFsgICAgMC4xNTQxODNdIGlteDZxLXBjaWUgMWZmYzAwMC5wY2llOiBQQ0kgaG9zdCBi
cmlkZ2UgdG8gYnVzDQo+IDAwMDA6MDANCj4gPiBbICAgIDAuMTU0MjAxXSBwY2lfYnVzIDAwMDA6
MDA6IHJvb3QgYnVzIHJlc291cmNlIFtidXMgMDAtZmZdDQo+ID4gWyAgICAwLjE1NDIxNV0gcGNp
X2J1cyAwMDAwOjAwOiByb290IGJ1cyByZXNvdXJjZSBbPz8/DQo+ID4gMHgwMWYwMDAwMC0weDAx
ZjdmZmZmIGZsYWdzIDB4MF0NCj4gPiBbICAgIDAuMTU0MjI4XSBwY2lfYnVzIDAwMDA6MDA6IHJv
b3QgYnVzIHJlc291cmNlIFtpbyAgMHgwMDAwLTB4ZmZmZl0NCj4gPiBbICAgIDAuMTU0MjcwXSBw
Y2lfYnVzIDAwMDA6MDA6IHJvb3QgYnVzIHJlc291cmNlIFttZW0gMHgwMTAwMDAwMC0NCj4gMHgw
MWVmZmZmZl0NCj4gPiBbICAgIDAuMTU0MzA2XSBwY2kgMDAwMDowMDowMC4wOiBbMTZjMzphYmNk
XSB0eXBlIDAxIGNsYXNzIDB4MDYwNDAwDQo+ID4gWyAgICAwLjE1NDMzM10gcGNpIDAwMDA6MDA6
MDAuMDogcmVnIDB4MTA6IFttZW0gMHgwMDAwMDAwMC0weDAwMGZmZmZmXQ0KPiA+IFsgICAgMC4x
NTQzNTJdIHBjaSAwMDAwOjAwOjAwLjA6IHJlZyAweDM4OiBbbWVtIDB4MDAwMDAwMDAtMHgwMDAw
ZmZmZg0KPiBwcmVmXQ0KPiA+IFsgICAgMC4xNTQzNzddIHBjaSAwMDAwOjAwOjAwLjA6IElPTU1V
IGlzIGN1cnJlbnRseSBub3Qgc3VwcG9ydGVkIGZvcg0KPiBQQ0kNCj4gPiBbICAgIDAuMTU0NDI5
XSBwY2kgMDAwMDowMDowMC4wOiBzdXBwb3J0cyBEMQ0KPiA+IFsgICAgMC4xNTQ0NDBdIHBjaSAw
MDAwOjAwOjAwLjA6IFBNRSMgc3VwcG9ydGVkIGZyb20gRDAgRDEgRDNob3QNCj4gRDNjb2xkDQo+
ID4gWyAgICAwLjE1NDY4M10gUENJOiBidXMwOiBGYXN0IGJhY2sgdG8gYmFjayB0cmFuc2ZlcnMg
ZGlzYWJsZWQNCj4gPiBbICAgIDAuMTU0ODA2XSBQQ0k6IGJ1czE6IEZhc3QgYmFjayB0byBiYWNr
IHRyYW5zZmVycyBlbmFibGVkDQo+ID4gWyAgICAwLjE1NDg4NF0gcGNpIDAwMDA6MDA6MDAuMDog
QkFSIDA6IGFzc2lnbmVkIFttZW0gMHgwMTAwMDAwMC0NCj4gMHgwMTBmZmZmZl0NCj4gPiBbICAg
IDAuMTU0OTAzXSBwY2kgMDAwMDowMDowMC4wOiBCQVIgNjogYXNzaWduZWQgW21lbSAweDAxMTAw
MDAwLQ0KPiAweDAxMTBmZmZmDQo+ID4gcHJlZl0NCj4gPiBbICAgIDAuMTU0OTE3XSBwY2kgMDAw
MDowMDowMC4wOiBQQ0kgYnJpZGdlIHRvIFtidXMgMDFdDQo+ID4gWyAgICAwLjE1NTE0NV0gcGNp
ZXBvcnQgMDAwMDowMDowMC4wOiBTaWduYWxpbmcgUE1FIHRocm91Z2ggUENJZSBQTUUNCj4gaW50
ZXJydXB0DQo+ID4gWyAgICAwLjE1NTE2MV0gcGNpZV9wbWUgMDAwMDowMDowMC4wOnBjaWUwMTog
c2VydmljZSBkcml2ZXIgcGNpZV9wbWUNCj4gbG9hZGVkDQo+ID4gWyAgICAwLjE1NTI3OV0gYWVy
IDAwMDA6MDA6MDAuMDpwY2llMDI6IHNlcnZpY2UgZHJpdmVyIGFlciBsb2FkZWQNCj4gPiBbICAg
IDEuMTg4ODQwXSBlaGNpLXBjaTogRUhDSSBQQ0kgcGxhdGZvcm0gZHJpdmVyDQo+ID4gWyAgICAx
LjIzMjUxOF0gb2hjaS1wY2k6IE9IQ0kgUENJIHBsYXRmb3JtIGRyaXZlcg0KPiA+DQo+ID4gLS0N
Cj4gPiBUbyB1bnN1YnNjcmliZSBmcm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJz
Y3JpYmUgbGludXgtcGNpIg0KPiBpbg0KPiA+IHRoZSBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpv
cmRvbW9Admdlci5rZXJuZWwub3JnDQo+ID4gTW9yZSBtYWpvcmRvbW8gaW5mbyBhdCAgaHR0cDov
L3ZnZXIua2VybmVsLm9yZy9tYWpvcmRvbW8taW5mby5odG1sDQo+ID4NCj4gPiAuDQo+ID4NCj4g
DQoNCg==

Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support

[Zhou Wang]

On 2015/7/10 16:53, Gabriele Paoloni wrote:
> I have just sent this patch "[PATCH] Store PCIe controllers address in struct of_pci_range".
> 
> It would be needed by "pcie_designware.c" to retrieve the PCI controller addresses from "win->__res.start".
> 
> So we do not need to retrieve info from the DT parser anymore and we can use the new PCI DT parsing API
> 
> This problem was already discussed in this thread:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/317743.html
> 
> 

Hi Gab,

Thanks for your patch.

That means I can use something like: pp->io_mod_base = win->__res.start
to get io_mod_base, mem_mod_base and cfg0_mod_base.

will send my v4 series based on your patch.

Best regards,
Zhou

>> -----Original Message-----
>> From: Wangzhou (B)
>> Sent: Tuesday, July 07, 2015 4:44 AM
>> To: James Morse
>> Cc: Gabriele Paoloni; Bjorn Helgaas; Jingoo Han; Pratyush Anand; Arnd
>> Bergmann; Liviu Dudau; kishon@ti.com; xobs@kosagi.com; m-
>> karicheri2@ti.com; Minghuan.Lian@freescale.com; linux-
>> pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo;
>> qiuzhenfa; Liguozhu (Kenneth)
>> Subject: Re: [PATCH v3 2/5] PCI: designware: Add ARM64 support
>>
>> On 2015/7/1 22:26, James Morse wrote:
>>> Zhou Wang wrote:
>>>> I tested this patch on D02 board of Hisilicon. It works well.
>>>> I have compiled the driver with multi_v7_defconfig. However, I don't
>>>> have
>>>> ARM32 PCIe related board to do test. It will be appreciated if
>> someone
>>>> could
>>>> help to test it.
>>>>
>>>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>>>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>>>> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
>>>> Tested-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>>>> Tested-by: James Morse <james.morse@arm.com>
>>>
>>> Tests on this new series, using the same i.MX 6Quad board, are not
>> working.
>>>
>>> The network card is no longer detected, and I get a lockup when
>> removing
>>> the root bridge and rescanning.
>>>
>>> Partial dmesg output below. Significantly, the lines:
>>>> [    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
>>>> [    0.152142]   No bus range found for /soc/pcie@0x01000000, using
>> [bus
>>> 00-ff]
>>> are new.
>>>
>>> Both series are applied to v4.1, use the same .config file, and the
>> same dtb.
>>> I will investigate further.
>>>
>>> (Re-testing v2 works, so this isn't an interim hardware failure)
>>>
>>> Thanks,
>>>
>>> James
>>>
>>
>> Hi James,
>>
>> There are something wrong with v3 patch.
>>
>> pp->io_mod_base = of_read_number(parser_range_end -
>> 		of_n_addr_cells(np) - 5 + na, ns);
>> pp->mem_mod_base = of_read_number(parser_range_end -
>> 		of_n_addr_cells(np) - 5 + na, ns);
>> pp->cfg0_mod_base = of_read_number(parser_range_end -
>> 		of_n_addr_cells(np) - 5 + na, ns);
>> are wrong.
>>
>> The ranges item in your dts is:
>> ranges = <0x800 0x0 0x1f00000 0x1f00000 0x0 0x80000
>> 	  0x81000000 0x0 0x0  0x1f80000 0x0 0x10000
>> 	  0x82000000 0x0 0x1000000 0x1000000 0x0 0xf00000>;
>> parser_range_end points to the end of ranges(0xf00000) directly. In v2
>> patch,
>> of_read_number is of_read_number(parser.range - parser.np + na, ns);
>> parser.range
>> points to the end of each line in ranges item.
>>
>> When I did test on D02 board with intel82599 card, I set ranges item as:
>> ranges = <0x03000000 0 0xb0000000 0x220 0x00000000 0 0xf000000>;
>> It is just one line. In this case, parser_range_end is same with
>> parser.range.
>> That is why it happened to work well on D02 board.
>>
>> very sorry to bother you about this problem.
>>
>> Thanks,
>> Zhou
>>
>>>
>>>
>>> root@localhost:~# dmesg | grep -i pci
>>> [    0.126184] PCI: CLS 0 bytes, default 64
>>> [    0.152128] PCI host bridge /soc/pcie@0x01000000 ranges:
>>> [    0.152142]   No bus range found for /soc/pcie@0x01000000, using
>> [bus 00-ff]
>>> [    0.154183] imx6q-pcie 1ffc000.pcie: PCI host bridge to bus
>> 0000:00
>>> [    0.154201] pci_bus 0000:00: root bus resource [bus 00-ff]
>>> [    0.154215] pci_bus 0000:00: root bus resource [???
>>> 0x01f00000-0x01f7ffff flags 0x0]
>>> [    0.154228] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
>>> [    0.154270] pci_bus 0000:00: root bus resource [mem 0x01000000-
>> 0x01efffff]
>>> [    0.154306] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
>>> [    0.154333] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
>>> [    0.154352] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff
>> pref]
>>> [    0.154377] pci 0000:00:00.0: IOMMU is currently not supported for
>> PCI
>>> [    0.154429] pci 0000:00:00.0: supports D1
>>> [    0.154440] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
>> D3cold
>>> [    0.154683] PCI: bus0: Fast back to back transfers disabled
>>> [    0.154806] PCI: bus1: Fast back to back transfers enabled
>>> [    0.154884] pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-
>> 0x010fffff]
>>> [    0.154903] pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-
>> 0x0110ffff
>>> pref]
>>> [    0.154917] pci 0000:00:00.0: PCI bridge to [bus 01]
>>> [    0.155145] pcieport 0000:00:00.0: Signaling PME through PCIe PME
>> interrupt
>>> [    0.155161] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme
>> loaded
>>> [    0.155279] aer 0000:00:00.0:pcie02: service driver aer loaded
>>> [    1.188840] ehci-pci: EHCI PCI platform driver
>>> [    1.232518] ohci-pci: OHCI PCI platform driver
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pci"
>> in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>> .
>>>
>>
> 

RE: [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Gabriele Paoloni]

VGhlIGZvbGxvd2luZyBwYXRjaCBpcyBtYXliZSBhIGJldHRlciBzb2x1dGlvbg0KDQpHYWINCg0K
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0NClRoaXMgcGF0Y2ggaXMgbmVlZGVkIGluIG9yZGVyIHRv
IHVuaWZ5IHRoZSBQQ0llIGRlc2lnbndhcmUNCmZyYW1ld29yayBmb3IgQVJNIGFuZCBBUk02NCBh
cmNoaXRlY3R1cmVzLg0KSW4gdGhlIFBDSWUgZGVzaWdud2FyZSB1bmlmaWNhdGlvbiBwcm9jZXNz
IHdlIGFyZSBjYWxsaW5nDQpwY2lfY3JlYXRlX3Jvb3RfYnVzKCkgcGFzc2luZyBhICJzeXNkYXRh
IiBwYXJhbWV0ZXINCnRoYXQgaXMgdGhlIHNhbWUgZm9yIGJvdGggQVJNIGFuZCBBUk02NCBhbmQg
aXMgb2YgdHlwZQ0KInN0cnVjdCBwY2llX3BvcnQqIi4gSW4gdGhlIEFSTSBjYXNlIHRoaXMgd2ls
bCBjYXVzZQ0KYSBwcm9ibGVtIHdpdGggdGhlIGZ1bmN0aW9uIHBjaWJpb3NfYWxpZ25fcmVzb3Vy
Y2UoKTsNCmluIGZhY3QgdGhpcyB3aWxsIGNhc3QgImRldi0+c3lzZGF0YSIgdG8gInN0cnVjdCBw
Y2lfc3lzX2RhdGEqIiwNCndoZXJlYXMgZGVzaWdud2FyZSBoYWQgcGFzc2VkIGEgInN0cnVjdCBw
Y2llX3BvcnQqIiBwb2ludGVyLg0KDQpUaGlzIHBhdGNoIHNvbHZlcyB0aGUgaXNzdWUgYnkgcmVt
b3ZpbmcgImFsaWduX3Jlc291cmNlIiBmcm9tDQoicGNpX3N5c19kYXRhIiBzdHJ1Y3QgYW5kIGRl
ZmluaW5nIGEgc3RhdGljIGdsb2JhbCBmdW5jdGlvbiBwb2ludGVyDQppbiAiYmlvczMyLmMiDQoN
ClNpZ25lZC1vZmYtYnk6IEdhYnJpZWxlIFBhb2xvbmkgPGdhYnJpZWxlLnBhb2xvbmkgYXQgaHVh
d2VpLmNvbT4NCi0tLQ0KIGFyY2gvYXJtL2luY2x1ZGUvYXNtL21hY2gvcGNpLmggfCAgNSAtLS0t
LQ0KIGFyY2gvYXJtL2tlcm5lbC9iaW9zMzIuYyAgICAgICAgfCAxMiArKysrKysrKy0tLS0NCiAy
IGZpbGVzIGNoYW5nZWQsIDggaW5zZXJ0aW9ucygrKSwgOSBkZWxldGlvbnMoLSkNCg0KZGlmZiAt
LWdpdCBhL2FyY2gvYXJtL2luY2x1ZGUvYXNtL21hY2gvcGNpLmggYi9hcmNoL2FybS9pbmNsdWRl
L2FzbS9tYWNoL3BjaS5oDQppbmRleCAyOGI5YmIzLi44YTRlNGRlIDEwMDY0NA0KLS0tIGEvYXJj
aC9hcm0vaW5jbHVkZS9hc20vbWFjaC9wY2kuaA0KKysrIGIvYXJjaC9hcm0vaW5jbHVkZS9hc20v
bWFjaC9wY2kuaA0KQEAgLTU4LDExICs1OCw2IEBAIHN0cnVjdCBwY2lfc3lzX2RhdGEgew0KIAkJ
CQkJLyogSVJRIG1hcHBpbmcJCQkJKi8NCiAJaW50CQkoKm1hcF9pcnEpKGNvbnN0IHN0cnVjdCBw
Y2lfZGV2ICosIHU4LCB1OCk7DQogCQkJCQkvKiBSZXNvdXJjZSBhbGlnbmVtZW50IHJlcXVpcmVt
ZW50cwkqLw0KLQlyZXNvdXJjZV9zaXplX3QgKCphbGlnbl9yZXNvdXJjZSkoc3RydWN0IHBjaV9k
ZXYgKmRldiwNCi0JCQkJCSAgY29uc3Qgc3RydWN0IHJlc291cmNlICpyZXMsDQotCQkJCQkgIHJl
c291cmNlX3NpemVfdCBzdGFydCwNCi0JCQkJCSAgcmVzb3VyY2Vfc2l6ZV90IHNpemUsDQotCQkJ
CQkgIHJlc291cmNlX3NpemVfdCBhbGlnbik7DQogCXZvaWQJCSpwcml2YXRlX2RhdGE7CS8qIHBs
YXRmb3JtIGNvbnRyb2xsZXIgcHJpdmF0ZSBkYXRhCSovDQogfTsNCiANCmRpZmYgLS1naXQgYS9h
cmNoL2FybS9rZXJuZWwvYmlvczMyLmMgYi9hcmNoL2FybS9rZXJuZWwvYmlvczMyLmMNCmluZGV4
IGZjYmJiYjEuLjRjZGM2NGQgMTAwNjQ0DQotLS0gYS9hcmNoL2FybS9rZXJuZWwvYmlvczMyLmMN
CisrKyBiL2FyY2gvYXJtL2tlcm5lbC9iaW9zMzIuYw0KQEAgLTE3LDYgKzE3LDExIEBADQogI2lu
Y2x1ZGUgPGFzbS9tYWNoL3BjaS5oPg0KIA0KIHN0YXRpYyBpbnQgZGVidWdfcGNpOw0KK3N0YXRp
YyByZXNvdXJjZV9zaXplX3QgKCphbGlnbl9yZXNvdXJjZSkoc3RydWN0IHBjaV9kZXYgKmRldiwN
CisJCSAgY29uc3Qgc3RydWN0IHJlc291cmNlICpyZXMsDQorCQkgIHJlc291cmNlX3NpemVfdCBz
dGFydCwNCisJCSAgcmVzb3VyY2Vfc2l6ZV90IHNpemUsDQorCQkgIHJlc291cmNlX3NpemVfdCBh
bGlnbikgPSBOVUxMOw0KIA0KICNpZmRlZiBDT05GSUdfUENJX01TSQ0KIHN0cnVjdCBtc2lfY29u
dHJvbGxlciAqcGNpYmlvc19tc2lfY29udHJvbGxlcihzdHJ1Y3QgcGNpX2RldiAqZGV2KQ0KQEAg
LTQ2OCw3ICs0NzMsNyBAQCBzdGF0aWMgdm9pZCBwY2liaW9zX2luaXRfaHcoc3RydWN0IGRldmlj
ZSAqcGFyZW50LCBzdHJ1Y3QgaHdfcGNpICpodywNCiAJCXN5cy0+YnVzbnIgICA9IGJ1c25yOw0K
IAkJc3lzLT5zd2l6emxlID0gaHctPnN3aXp6bGU7DQogCQlzeXMtPm1hcF9pcnEgPSBody0+bWFw
X2lycTsNCi0JCXN5cy0+YWxpZ25fcmVzb3VyY2UgPSBody0+YWxpZ25fcmVzb3VyY2U7DQorCQlh
bGlnbl9yZXNvdXJjZSA9IGh3LT5hbGlnbl9yZXNvdXJjZTsNCiAJCUlOSVRfTElTVF9IRUFEKCZz
eXMtPnJlc291cmNlcyk7DQogDQogCQlpZiAoaHctPnByaXZhdGVfZGF0YSkNCkBAIC01ODksNyAr
NTk0LDYgQEAgcmVzb3VyY2Vfc2l6ZV90IHBjaWJpb3NfYWxpZ25fcmVzb3VyY2Uodm9pZCAqZGF0
YSwgY29uc3Qgc3RydWN0IHJlc291cmNlICpyZXMsDQogCQkJCXJlc291cmNlX3NpemVfdCBzaXpl
LCByZXNvdXJjZV9zaXplX3QgYWxpZ24pDQogew0KIAlzdHJ1Y3QgcGNpX2RldiAqZGV2ID0gZGF0
YTsNCi0Jc3RydWN0IHBjaV9zeXNfZGF0YSAqc3lzID0gZGV2LT5zeXNkYXRhOw0KIAlyZXNvdXJj
ZV9zaXplX3Qgc3RhcnQgPSByZXMtPnN0YXJ0Ow0KIA0KIAlpZiAocmVzLT5mbGFncyAmIElPUkVT
T1VSQ0VfSU8gJiYgc3RhcnQgJiAweDMwMCkNCkBAIC01OTcsOCArNjAxLDggQEAgcmVzb3VyY2Vf
c2l6ZV90IHBjaWJpb3NfYWxpZ25fcmVzb3VyY2Uodm9pZCAqZGF0YSwgY29uc3Qgc3RydWN0IHJl
c291cmNlICpyZXMsDQogDQogCXN0YXJ0ID0gKHN0YXJ0ICsgYWxpZ24gLSAxKSAmIH4oYWxpZ24g
LSAxKTsNCiANCi0JaWYgKHN5cy0+YWxpZ25fcmVzb3VyY2UpDQotCQlyZXR1cm4gc3lzLT5hbGln
bl9yZXNvdXJjZShkZXYsIHJlcywgc3RhcnQsIHNpemUsIGFsaWduKTsNCisJaWYgKGFsaWduX3Jl
c291cmNlKQ0KKwkJcmV0dXJuIGFsaWduX3Jlc291cmNlKGRldiwgcmVzLCBzdGFydCwgc2l6ZSwg
YWxpZ24pOw0KIA0KIAlyZXR1cm4gc3RhcnQ7DQogfQ0KLS0gDQoxLjkuMQ0KDQo+IC0tLS0tT3Jp
Z2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IGxpbnV4LXBjaS1vd25lckB2Z2VyLmtlcm5lbC5v
cmcgW21haWx0bzpsaW51eC1wY2ktDQo+IG93bmVyQHZnZXIua2VybmVsLm9yZ10gT24gQmVoYWxm
IE9mIExpdml1IER1ZGF1DQo+IFNlbnQ6IFR1ZXNkYXksIEp1bHkgMDcsIDIwMTUgMTA6MjIgQU0N
Cj4gVG86IFdhbmd6aG91IChCKQ0KPiBDYzogQmpvcm4gSGVsZ2FhczsgSmluZ29vIEhhbjsgUHJh
dHl1c2ggQW5hbmQ7IEFybmQgQmVyZ21hbm47IEdhYnJpZWxlDQo+IFBhb2xvbmk7IEphbWVzIE1v
cnNlOyBsaW51eC1wY2lAdmdlci5rZXJuZWwub3JnOyBsaW51eC1hcm0tDQo+IGtlcm5lbEBsaXN0
cy5pbmZyYWRlYWQub3JnOyBkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZzsgWXVhbnpoaWNoYW5n
Ow0KPiBaaHVkYWNhaTsgemhhbmdqdWt1bzsgcWl1emhlbmZhOyBMaWd1b3podSAoS2VubmV0aCkN
Cj4gU3ViamVjdDogUmU6IFtQQVRDSCB2MyAxLzVdIEFSTS9QQ0k6IHJlbW92ZSBhbGlnbl9yZXNv
dXJjZSBjYWxsYmFjayBpbg0KPiBwY2liaW9zX2FsaWduX3Jlc291cmNlDQo+IA0KPiBPbiBUdWUs
IEp1bCAwNywgMjAxNSBhdCAwNjo0NDowMUFNICswMTAwLCBaaG91IFdhbmcgd3JvdGU6DQo+ID4g
T24gMjAxNS83LzMgMTo1MCwgTGl2aXUgRHVkYXUgd3JvdGU6DQo+ID4gPiBPbiBXZWQsIEp1bCAw
MSwgMjAxNSBhdCAxMDo0MzozM0FNICswMTAwLCBaaG91IFdhbmcgd3JvdGU6DQo+ID4gPj4gVGhp
cyBwYXRjaCBoYWQgYWRkZWQgYnkgQXJuZCBCZXJnbWFubiBkdXJpbmcgbGFzdCByZXZpZXdpbmcg
b2YgdjENCj4gcGF0Y2hzZXRbMV0uDQo+ID4gPj4NCj4gPiA+PiBQQ0kgY29yZSBjb2RlcyBjYWxs
IHBjaWJpb3NfYWxpZ25fcmVzb3VyY2UoKS4gSW4gQVJNIHNwZWNpZmljIG9uZSwNCj4gaXQgd2ls
bA0KPiA+ID4+IGRlcmVmZXJlbmNlIHBjaV9zeXNfZGF0YSBhbmQgY2FsbCBzeXMtPmFsaWduX3Jl
c291cmNlLiBJZiB3ZSB0cnkNCj4gdG8gdW5pZnkgQVJNDQo+ID4gPj4gYW5kIEFSTTY0IFBDSWUg
QVBJIGluIHBjaWUtZGVzaWdud2FyZS4gaXQgd2lsbCBicmluZyBrZXJuZWwgY3Jhc2gNCj4gd2hl
biBydW4gaW50bw0KPiA+ID4+IHRoaXMgZGVyZWZlcmVuY2luZy4NCj4gPiA+Pg0KPiA+ID4+IEhv
d2V2ZXIsIGluIEFSTSB0aGVyZSBpcyBvbmx5IHBjaS1tdmVidSB3aGljaCBpbXBsZW1lbnRzDQo+
IGFsaWduX3Jlc291cmNlLiBTbw0KPiA+ID4+IGFkZCBhbGlnbl9yZXNvdXJjZSBjYWxsIGJhY2sg
aW4gcGNpX2hvc3RfYnJpZGdlIHN0cnVjdHVyZSBhbmQNCj4gb3ZlcnJpZGUNCj4gPiA+PiBwY2li
aW9zX2FsaWduX3Jlc291cmNlIHdpdGggaXQuDQo+ID4gPj4NCj4gPiA+PiBTaWduZWQtb2ZmLWJ5
OiBBcm5kIEJlcmdtYW5uIDxhcm5kQGFybmRiLmRlPg0KPiA+ID4+IFNpZ25lZC1vZmYtYnk6IFpo
b3UgV2FuZyA8d2FuZ3pob3UxQGhpc2lsaWNvbi5jb20+DQo+ID4gPj4gVGVzdGVkLWJ5OiBGYWJy
aWNlIEdhc25pZXIgPGZhYnJpY2UuZ2FzbmllckBzdC5jb20+DQo+ID4gPj4NCj4gPiA+PiBbMV0g
aHR0cDovL3d3dy5zcGluaWNzLm5ldC9saXN0cy9saW51eC1wY2kvbXNnNDE2NzEuaHRtbA0KPiA+
ID4+IC0tLQ0KPiA+ID4+ICBhcmNoL2FybS9rZXJuZWwvYmlvczMyLmMgICAgIHwgIDYgLS0tLS0t
DQo+ID4gPj4gIGRyaXZlcnMvcGNpL2hvc3QvcGNpLW12ZWJ1LmMgfCA0NyArKysrKysrKysrKysr
KysrKysrKysrKysrKysrLS0tDQo+IC0tLS0tLS0tLS0tLS0NCj4gPiA+PiAgZHJpdmVycy9wY2kv
c2V0dXAtcmVzLmMgICAgICB8IDI3ICsrKysrKysrKysrKysrKysrKysrLS0tLS0NCj4gPiA+PiAg
aW5jbHVkZS9saW51eC9wY2kuaCAgICAgICAgICB8ICAzICsrKw0KPiA+ID4+ICA0IGZpbGVzIGNo
YW5nZWQsIDU1IGluc2VydGlvbnMoKyksIDI4IGRlbGV0aW9ucygtKQ0KPiA+ID4+DQo+ID4gPj4g
ZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2tlcm5lbC9iaW9zMzIuYyBiL2FyY2gvYXJtL2tlcm5lbC9i
aW9zMzIuYw0KPiA+ID4+IGluZGV4IGZjYmJiYjEuLmIwMTE4OWYgMTAwNjQ0DQo+ID4gPj4gLS0t
IGEvYXJjaC9hcm0va2VybmVsL2Jpb3MzMi5jDQo+ID4gPj4gKysrIGIvYXJjaC9hcm0va2VybmVs
L2Jpb3MzMi5jDQo+ID4gPj4gQEAgLTQ2OCw3ICs0NjgsNiBAQCBzdGF0aWMgdm9pZCBwY2liaW9z
X2luaXRfaHcoc3RydWN0IGRldmljZQ0KPiAqcGFyZW50LCBzdHJ1Y3QgaHdfcGNpICpodywNCj4g
PiA+PiAgCQlzeXMtPmJ1c25yICAgPSBidXNucjsNCj4gPiA+PiAgCQlzeXMtPnN3aXp6bGUgPSBo
dy0+c3dpenpsZTsNCj4gPiA+PiAgCQlzeXMtPm1hcF9pcnEgPSBody0+bWFwX2lycTsNCj4gPiA+
PiAtCQlzeXMtPmFsaWduX3Jlc291cmNlID0gaHctPmFsaWduX3Jlc291cmNlOw0KPiA+ID4+ICAJ
CUlOSVRfTElTVF9IRUFEKCZzeXMtPnJlc291cmNlcyk7DQo+ID4gPj4NCj4gPiA+PiAgCQlpZiAo
aHctPnByaXZhdGVfZGF0YSkNCj4gPiA+PiBAQCAtNTg4LDggKzU4Nyw2IEBAIGNoYXIgKiBfX2lu
aXQgcGNpYmlvc19zZXR1cChjaGFyICpzdHIpDQo+ID4gPj4gIHJlc291cmNlX3NpemVfdCBwY2li
aW9zX2FsaWduX3Jlc291cmNlKHZvaWQgKmRhdGEsIGNvbnN0IHN0cnVjdA0KPiByZXNvdXJjZSAq
cmVzLA0KPiA+ID4+ICAJCQkJcmVzb3VyY2Vfc2l6ZV90IHNpemUsIHJlc291cmNlX3NpemVfdA0K
PiBhbGlnbikNCj4gPiA+PiAgew0KPiA+ID4+IC0Jc3RydWN0IHBjaV9kZXYgKmRldiA9IGRhdGE7
DQo+ID4gPj4gLQlzdHJ1Y3QgcGNpX3N5c19kYXRhICpzeXMgPSBkZXYtPnN5c2RhdGE7DQo+ID4g
Pj4gIAlyZXNvdXJjZV9zaXplX3Qgc3RhcnQgPSByZXMtPnN0YXJ0Ow0KPiA+ID4+DQo+ID4gPj4g
IAlpZiAocmVzLT5mbGFncyAmIElPUkVTT1VSQ0VfSU8gJiYgc3RhcnQgJiAweDMwMCkNCj4gPiA+
PiBAQCAtNTk3LDkgKzU5NCw2IEBAIHJlc291cmNlX3NpemVfdCBwY2liaW9zX2FsaWduX3Jlc291
cmNlKHZvaWQNCj4gKmRhdGEsIGNvbnN0IHN0cnVjdCByZXNvdXJjZSAqcmVzLA0KPiA+ID4+DQo+
ID4gPj4gIAlzdGFydCA9IChzdGFydCArIGFsaWduIC0gMSkgJiB+KGFsaWduIC0gMSk7DQo+ID4g
Pj4NCj4gPiA+PiAtCWlmIChzeXMtPmFsaWduX3Jlc291cmNlKQ0KPiA+ID4+IC0JCXJldHVybiBz
eXMtPmFsaWduX3Jlc291cmNlKGRldiwgcmVzLCBzdGFydCwgc2l6ZSwNCj4gYWxpZ24pOw0KPiA+
ID4+IC0NCj4gPiA+PiAgCXJldHVybiBzdGFydDsNCj4gPiA+PiAgfQ0KPiA+ID4+DQo+ID4gPj4g
ZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2hvc3QvcGNpLW12ZWJ1LmMgYi9kcml2ZXJzL3BjaS9o
b3N0L3BjaS0NCj4gbXZlYnUuYw0KPiA+ID4+IGluZGV4IDFhYjg2MzUuLjE1NWQwNWYgMTAwNjQ0
DQo+ID4gPj4gLS0tIGEvZHJpdmVycy9wY2kvaG9zdC9wY2ktbXZlYnUuYw0KPiA+ID4+ICsrKyBi
L2RyaXZlcnMvcGNpL2hvc3QvcGNpLW12ZWJ1LmMNCj4gPiA+PiBAQCAtMjIsNiArMjIsOCBAQA0K
PiA+ID4+ICAjaW5jbHVkZSA8bGludXgvb2ZfcGNpLmg+DQo+ID4gPj4gICNpbmNsdWRlIDxsaW51
eC9vZl9wbGF0Zm9ybS5oPg0KPiA+ID4+DQo+ID4gPj4gKyNpbmNsdWRlICIuLi9wY2kuaCIgLyog
SEFDSyB0byBzZWUgcGNpX2ZpbmRfaG9zdF9icmlkZ2UgKi8NCj4gPiA+PiArDQo+ID4gPj4gIC8q
DQo+ID4gPj4gICAqIFBDSWUgdW5pdCByZWdpc3RlciBvZmZzZXRzLg0KPiA+ID4+ICAgKi8NCj4g
PiA+PiBAQCAtNzUxLDI3ICs3NTMsMjAgQEAgc3RhdGljIGludCBtdmVidV9wY2llX3NldHVwKGlu
dCBuciwgc3RydWN0DQo+IHBjaV9zeXNfZGF0YSAqc3lzKQ0KPiA+ID4+ICAJcmV0dXJuIDE7DQo+
ID4gPj4gIH0NCj4gPiA+Pg0KPiA+ID4+IC1zdGF0aWMgc3RydWN0IHBjaV9idXMgKm12ZWJ1X3Bj
aWVfc2Nhbl9idXMoaW50IG5yLCBzdHJ1Y3QNCj4gcGNpX3N5c19kYXRhICpzeXMpDQo+ID4gPj4g
K3N0YXRpYyByZXNvdXJjZV9zaXplX3QgbXZlYnVfcGNpZV9hbGlnbl9yZXNvdXJjZSh2b2lkICpk
YXRhLA0KPiA+ID4+ICsJCQkJCQkgY29uc3Qgc3RydWN0IHJlc291cmNlICpyZXMsDQo+ID4gPj4g
KwkJCQkJCSByZXNvdXJjZV9zaXplX3Qgc2l6ZSwNCj4gPiA+PiArCQkJCQkJIHJlc291cmNlX3Np
emVfdCBhbGlnbikNCj4gPiA+PiAgew0KPiA+ID4+IC0Jc3RydWN0IG12ZWJ1X3BjaWUgKnBjaWUg
PSBzeXNfdG9fcGNpZShzeXMpOw0KPiA+ID4+IC0Jc3RydWN0IHBjaV9idXMgKmJ1czsNCj4gPiA+
PiArCXN0cnVjdCBwY2lfZGV2ICpkZXYgPSBkYXRhOw0KPiA+ID4+DQo+ID4gPj4gLQlidXMgPSBw
Y2lfY3JlYXRlX3Jvb3RfYnVzKCZwY2llLT5wZGV2LT5kZXYsIHN5cy0+YnVzbnIsDQo+ID4gPj4g
LQkJCQkgICZtdmVidV9wY2llX29wcywgc3lzLCAmc3lzLT5yZXNvdXJjZXMpOw0KPiA+ID4+IC0J
aWYgKCFidXMpDQo+ID4gPj4gLQkJcmV0dXJuIE5VTEw7DQo+ID4gPj4gKwlyZXNvdXJjZV9zaXpl
X3Qgc3RhcnQgPSByZXMtPnN0YXJ0Ow0KPiA+ID4+DQo+ID4gPj4gLQlwY2lfc2Nhbl9jaGlsZF9i
dXMoYnVzKTsNCj4gPiA+PiArCWlmIChyZXMtPmZsYWdzICYgSU9SRVNPVVJDRV9JTyAmJiBzdGFy
dCAmIDB4MzAwKQ0KPiA+ID4+ICsJCXN0YXJ0ID0gKHN0YXJ0ICsgMHgzZmYpICYgfjB4M2ZmOw0K
PiA+ID4+DQo+ID4gPj4gLQlyZXR1cm4gYnVzOw0KPiA+ID4+IC19DQo+ID4gPj4gKwlzdGFydCA9
IChzdGFydCArIGFsaWduIC0gMSkgJiB+KGFsaWduIC0gMSk7DQo+ID4gPg0KPiA+ID4gSG9uZXN0
bHksIEkgZG9uJ3Qgc2VlIGhlcmUgYW55dGhpbmcgdGhhdCBpcyBtdmVidSBzcGVjaWZpYy4gQ291
bGQNCj4geW91IG1vdmUNCj4gPg0KPiA+IFdoYXQgSSBtZWFuIGlzIHRoYXQgdGhlcmUgaXMgb25s
eSBtdmVidSB3aG8gaW1wbGVtZW50ZWQgc3lzLQ0KPiA+YWxpZ25fcmVzb3VyY2UgY2FsbGJhY2sg
aW4gQVJNDQo+ID4gYXJjaC4NCj4gPg0KPiA+ID4gdGhpcyBmdW5jdGlvbiBpbiB0aGUgZ2VuZXJp
YyBwY2kvaG9zdCBhcmVhIGFuZCBoYXZlIGEgZmxhZyBpbiB0aGUNCj4gcGNpX2hvc3RfYnJpZGdl
DQo+ID4gPiBzdHJ1Y3R1cmUgd2hldGhlciB0aGUgZnVuY3Rpb24gc2hvdWxkIGJlIGNhbGxlZCBv
ciBub3Q/IEkga25vdyB0aGF0DQo+IGluIGEgd2F5DQo+ID4gPiB0aGF0IGxvb2tzIHZlcnkgY2xv
c2UgdG8gdGhlIGV4aXN0aW5nIGltcGxlbWVudGF0aW9uIHdoaWNoIHVzZXMNCj4gcGNpYmlvc19h
bGlnbl9yZXNvdXJjZSwNCj4gPg0KPiA+IEkgYW0gY29uZnVzZWQgYWJvdXQgInRoZSBleGlzdGlu
ZyBpbXBsZW1lbnRhdGlvbiIuIE5vdw0KPiBwY2liaW9zX2FsaWduX3Jlc291cmNlIGFyZQ0KPiA+
IGltcGxlbWVudGVkIGJ5IGVhY2ggYXJjaCBjb2RlIGFuZCBhcmUgY2FsbGVkIGRpcmVjdGx5LiBE
aWQgSSBtaXNzDQo+IGFueXRoaW5nIGFib3V0DQo+ID4gcGNpYmlvc19hbGlnbl9yZXNvdXJjZT8N
Cj4gDQo+IFNvcnJ5LCBJIG1lYW50IGV4aXN0aW5nIGltcGxlbWVudGF0aW9uX3NfIGFuZCB5ZXMs
IEkgd2FzIHJlZmZlcmluZyB0bw0KPiB0aGUgYXJjaCBzcGVjaWZpYw0KPiBjb2RlLiBJZiB5b3Ug
bG9vayBhdCB0aGUgY3JpcywgZnJ2L21iOTMwOTAtbWIwMCwgbTY4aywgbWljcm9ibGF6ZSwNCj4g
cG93ZXJwYywgdW5pY29yZTMyDQo+IGFuZCB4ODYgdGhleSBhbGwgc2hhcmUgdGhlIGNvZGUgd2l0
aCB5b3VyIHZlcnNpb24sIHBsdXMgb3IgbWludXMNCj4gYWRkaXRpb25hbCBjaGVja3MuDQo+IEkg
d2FzIHRoaW5raW5nIHRoYXQgZm9yIHRob3NlIGFyY2ggdmVyc2lvbnMgdGhhdCBtYXRjaCB5b3Vy
IHZlcnNpb24geW91DQo+IGNhbiBjcmVhdGUganVzdA0KPiBvbmUgdmVyc2lvbiBhbmQgdXNlIGl0
IGFzIHRoZSBhbGlnbmYgZnVuY3Rpb24uDQo+IA0KPiBCZXN0IHJlZ2FyZHMsDQo+IExpdml1DQo+
IA0KPiA+DQo+ID4gQmVzdCByZ2FyZHMsDQo+ID4gWmhvdQ0KPiA+DQo+ID4gPiBidXQgdGhlIHBy
b2JsZW0gd2l0aCBwY2liaW9zXyB2ZXJzaW9uIGlzIHRoYXQgaXQgaXMgYXJjaCBzcGVjaWZpYw0K
PiBhbmQgbm90IGRyaXZlcg0KPiA+ID4gc3BlY2lmaWMgdGhlIHdheSB3ZSB3YW50Lg0KPiA+ID4N
Cj4gPiA+IEhhdmluZyB0aGlzIHZlcnNpb24gYXMgYSBnZW5lcmljIGltcGxlbWVudGF0aW9uIHdv
dWxkIGFsc28gcmVtb3ZlDQo+IGF0IGxlYXN0IDIgbW9yZQ0KPiA+ID4gYXJjaCB2ZXJzaW9uLCBw
b3NzaWJseSBtb3JlIGFmdGVyIHRlc3RpbmcgYnkgdGhlIGFyY2ggbWFpbnRhaW5lcnMuDQo+ID4g
Pg0KPiA+ID4gQmVzdCByZWdhcmRzLA0KPiA+ID4gTGl2aXUNCj4gPiA+DQo+ID4gPj4NCj4gPiA+
PiAtc3RhdGljIHJlc291cmNlX3NpemVfdCBtdmVidV9wY2llX2FsaWduX3Jlc291cmNlKHN0cnVj
dCBwY2lfZGV2DQo+ICpkZXYsDQo+ID4gPj4gLQkJCQkJCSBjb25zdCBzdHJ1Y3QgcmVzb3VyY2Ug
KnJlcywNCj4gPiA+PiAtCQkJCQkJIHJlc291cmNlX3NpemVfdCBzdGFydCwNCj4gPiA+PiAtCQkJ
CQkJIHJlc291cmNlX3NpemVfdCBzaXplLA0KPiA+ID4+IC0JCQkJCQkgcmVzb3VyY2Vfc2l6ZV90
IGFsaWduKQ0KPiA+ID4+IC17DQo+ID4gPj4gIAlpZiAoZGV2LT5idXMtPm51bWJlciAhPSAwKQ0K
PiA+ID4+ICAJCXJldHVybiBzdGFydDsNCj4gPiA+Pg0KPiA+ID4+IEBAIC03OTYsNiArNzkxLDI1
IEBAIHN0YXRpYyByZXNvdXJjZV9zaXplX3QNCj4gbXZlYnVfcGNpZV9hbGlnbl9yZXNvdXJjZShz
dHJ1Y3QgcGNpX2RldiAqZGV2LA0KPiA+ID4+ICAJCXJldHVybiBzdGFydDsNCj4gPiA+PiAgfQ0K
PiA+ID4+DQo+ID4gPj4gK3N0YXRpYyBzdHJ1Y3QgcGNpX2J1cyAqbXZlYnVfcGNpZV9zY2FuX2J1
cyhpbnQgbnIsIHN0cnVjdA0KPiBwY2lfc3lzX2RhdGEgKnN5cykNCj4gPiA+PiArew0KPiA+ID4+
ICsJc3RydWN0IG12ZWJ1X3BjaWUgKnBjaWUgPSBzeXNfdG9fcGNpZShzeXMpOw0KPiA+ID4+ICsJ
c3RydWN0IHBjaV9ob3N0X2JyaWRnZSAqcGhiOw0KPiA+ID4+ICsJc3RydWN0IHBjaV9idXMgKmJ1
czsNCj4gPiA+PiArDQo+ID4gPj4gKwlidXMgPSBwY2lfY3JlYXRlX3Jvb3RfYnVzKCZwY2llLT5w
ZGV2LT5kZXYsIHN5cy0+YnVzbnIsDQo+ID4gPj4gKwkJCQkgICZtdmVidV9wY2llX29wcywgc3lz
LCAmc3lzLT5yZXNvdXJjZXMpOw0KPiA+ID4+ICsJaWYgKCFidXMpDQo+ID4gPj4gKwkJcmV0dXJu
IE5VTEw7DQo+ID4gPj4gKw0KPiA+ID4+ICsJcGhiID0gcGNpX2ZpbmRfaG9zdF9icmlkZ2UoYnVz
KTsNCj4gPiA+PiArCXBoYi0+YWxpZ25fcmVzb3VyY2UgPSBtdmVidV9wY2llX2FsaWduX3Jlc291
cmNlOw0KPiA+ID4+ICsNCj4gPiA+PiArCXBjaV9zY2FuX2NoaWxkX2J1cyhidXMpOw0KPiA+ID4+
ICsNCj4gPiA+PiArCXJldHVybiBidXM7DQo+ID4gPj4gK30NCj4gPiA+PiArDQo+ID4gPj4gIHN0
YXRpYyB2b2lkIG12ZWJ1X3BjaWVfZW5hYmxlKHN0cnVjdCBtdmVidV9wY2llICpwY2llKQ0KPiA+
ID4+ICB7DQo+ID4gPj4gIAlzdHJ1Y3QgaHdfcGNpIGh3Ow0KPiA+ID4+IEBAIC04MTIsNyArODI2
LDYgQEAgc3RhdGljIHZvaWQgbXZlYnVfcGNpZV9lbmFibGUoc3RydWN0DQo+IG12ZWJ1X3BjaWUg
KnBjaWUpDQo+ID4gPj4gIAlody5zY2FuICAgICAgICAgICA9IG12ZWJ1X3BjaWVfc2Nhbl9idXM7
DQo+ID4gPj4gIAlody5tYXBfaXJxICAgICAgICA9IG9mX2lycV9wYXJzZV9hbmRfbWFwX3BjaTsN
Cj4gPiA+PiAgCWh3Lm9wcyAgICAgICAgICAgID0gJm12ZWJ1X3BjaWVfb3BzOw0KPiA+ID4+IC0J
aHcuYWxpZ25fcmVzb3VyY2UgPSBtdmVidV9wY2llX2FsaWduX3Jlc291cmNlOw0KPiA+ID4+DQo+
ID4gPj4gIAlwY2lfY29tbW9uX2luaXQoJmh3KTsNCj4gPiA+PiAgfQ0KPiA+ID4+IGRpZmYgLS1n
aXQgYS9kcml2ZXJzL3BjaS9zZXR1cC1yZXMuYyBiL2RyaXZlcnMvcGNpL3NldHVwLXJlcy5jDQo+
ID4gPj4gaW5kZXggMjMyZjkyNS4uNzNhYmNhNyAxMDA2NDQNCj4gPiA+PiAtLS0gYS9kcml2ZXJz
L3BjaS9zZXR1cC1yZXMuYw0KPiA+ID4+ICsrKyBiL2RyaXZlcnMvcGNpL3NldHVwLXJlcy5jDQo+
ID4gPj4gQEAgLTIwMCw3ICsyMDAsMTEgQEAgc3RhdGljIGludCBwY2lfcmV2ZXJ0X2Z3X2FkZHJl
c3Moc3RydWN0DQo+IHJlc291cmNlICpyZXMsIHN0cnVjdCBwY2lfZGV2ICpkZXYsDQo+ID4gPj4g
IH0NCj4gPiA+Pg0KPiA+ID4+ICBzdGF0aWMgaW50IF9fcGNpX2Fzc2lnbl9yZXNvdXJjZShzdHJ1
Y3QgcGNpX2J1cyAqYnVzLCBzdHJ1Y3QNCj4gcGNpX2RldiAqZGV2LA0KPiA+ID4+IC0JCWludCBy
ZXNubywgcmVzb3VyY2Vfc2l6ZV90IHNpemUsIHJlc291cmNlX3NpemVfdA0KPiBhbGlnbikNCj4g
PiA+PiArCQlpbnQgcmVzbm8sIHJlc291cmNlX3NpemVfdCBzaXplLCByZXNvdXJjZV9zaXplX3QN
Cj4gYWxpZ24sDQo+ID4gPj4gKwkJcmVzb3VyY2Vfc2l6ZV90ICgqYWxpZ25mKSh2b2lkICosDQo+
ID4gPj4gKwkJCQkJICBjb25zdCBzdHJ1Y3QgcmVzb3VyY2UgKiwNCj4gPiA+PiArCQkJCQkgIHJl
c291cmNlX3NpemVfdCwNCj4gPiA+PiArCQkJCQkgIHJlc291cmNlX3NpemVfdCkpDQo+ID4gPj4g
IHsNCj4gPiA+PiAgCXN0cnVjdCByZXNvdXJjZSAqcmVzID0gZGV2LT5yZXNvdXJjZSArIHJlc25v
Ow0KPiA+ID4+ICAJcmVzb3VyY2Vfc2l6ZV90IG1pbjsNCj4gPiA+PiBAQCAtMjE3LDcgKzIyMSw3
IEBAIHN0YXRpYyBpbnQgX19wY2lfYXNzaWduX3Jlc291cmNlKHN0cnVjdA0KPiBwY2lfYnVzICpi
dXMsIHN0cnVjdCBwY2lfZGV2ICpkZXYsDQo+ID4gPj4gIAkgKi8NCj4gPiA+PiAgCXJldCA9IHBj
aV9idXNfYWxsb2NfcmVzb3VyY2UoYnVzLCByZXMsIHNpemUsIGFsaWduLCBtaW4sDQo+ID4gPj4g
IAkJCQkgICAgIElPUkVTT1VSQ0VfUFJFRkVUQ0ggfA0KPiBJT1JFU09VUkNFX01FTV82NCwNCj4g
PiA+PiAtCQkJCSAgICAgcGNpYmlvc19hbGlnbl9yZXNvdXJjZSwgZGV2KTsNCj4gPiA+PiArCQkJ
CSAgICAgYWxpZ25mLCBkZXYpOw0KPiA+ID4+ICAJaWYgKHJldCA9PSAwKQ0KPiA+ID4+ICAJCXJl
dHVybiAwOw0KPiA+ID4+DQo+ID4gPj4gQEAgLTIyOSw3ICsyMzMsNyBAQCBzdGF0aWMgaW50IF9f
cGNpX2Fzc2lnbl9yZXNvdXJjZShzdHJ1Y3QNCj4gcGNpX2J1cyAqYnVzLCBzdHJ1Y3QgcGNpX2Rl
diAqZGV2LA0KPiA+ID4+ICAJICAgICAoSU9SRVNPVVJDRV9QUkVGRVRDSCB8IElPUkVTT1VSQ0Vf
TUVNXzY0KSkgew0KPiA+ID4+ICAJCXJldCA9IHBjaV9idXNfYWxsb2NfcmVzb3VyY2UoYnVzLCBy
ZXMsIHNpemUsIGFsaWduLA0KPiBtaW4sDQo+ID4gPj4gIAkJCQkJICAgICBJT1JFU09VUkNFX1BS
RUZFVENILA0KPiA+ID4+IC0JCQkJCSAgICAgcGNpYmlvc19hbGlnbl9yZXNvdXJjZSwgZGV2KTsN
Cj4gPiA+PiArCQkJCQkgICAgIGFsaWduZiwgZGV2KTsNCj4gPiA+PiAgCQlpZiAocmV0ID09IDAp
DQo+ID4gPj4gIAkJCXJldHVybiAwOw0KPiA+ID4+ICAJfQ0KPiA+ID4+IEBAIC0yNDIsNyArMjQ2
LDcgQEAgc3RhdGljIGludCBfX3BjaV9hc3NpZ25fcmVzb3VyY2Uoc3RydWN0DQo+IHBjaV9idXMg
KmJ1cywgc3RydWN0IHBjaV9kZXYgKmRldiwNCj4gPiA+PiAgCSAqLw0KPiA+ID4+ICAJaWYgKHJl
cy0+ZmxhZ3MgJiAoSU9SRVNPVVJDRV9QUkVGRVRDSCB8IElPUkVTT1VSQ0VfTUVNXzY0KSkNCj4g
PiA+PiAgCQlyZXQgPSBwY2lfYnVzX2FsbG9jX3Jlc291cmNlKGJ1cywgcmVzLCBzaXplLCBhbGln
biwNCj4gbWluLCAwLA0KPiA+ID4+IC0JCQkJCSAgICAgcGNpYmlvc19hbGlnbl9yZXNvdXJjZSwg
ZGV2KTsNCj4gPiA+PiArCQkJCQkgICAgIGFsaWduZiwgZGV2KTsNCj4gPiA+Pg0KPiA+ID4+ICAJ
cmV0dXJuIHJldDsNCj4gPiA+PiAgfQ0KPiA+ID4+IEBAIC0yNTEsMTAgKzI1NSwyMyBAQCBzdGF0
aWMgaW50IF9wY2lfYXNzaWduX3Jlc291cmNlKHN0cnVjdA0KPiBwY2lfZGV2ICpkZXYsIGludCBy
ZXNubywNCj4gPiA+PiAgCQkJCXJlc291cmNlX3NpemVfdCBzaXplLCByZXNvdXJjZV9zaXplX3QN
Cj4gbWluX2FsaWduKQ0KPiA+ID4+ICB7DQo+ID4gPj4gIAlzdHJ1Y3QgcGNpX2J1cyAqYnVzOw0K
PiA+ID4+ICsJc3RydWN0IHBjaV9ob3N0X2JyaWRnZSAqcGhiOw0KPiA+ID4+ICsJcmVzb3VyY2Vf
c2l6ZV90ICgqYWxpZ25mKSh2b2lkICosDQo+ID4gPj4gKwkJCQkgIGNvbnN0IHN0cnVjdCByZXNv
dXJjZSAqLA0KPiA+ID4+ICsJCQkJICByZXNvdXJjZV9zaXplX3QsDQo+ID4gPj4gKwkJCQkgIHJl
c291cmNlX3NpemVfdCk7DQo+ID4gPj4gIAlpbnQgcmV0Ow0KPiA+ID4+DQo+ID4gPj4gIAlidXMg
PSBkZXYtPmJ1czsNCj4gPiA+PiAtCXdoaWxlICgocmV0ID0gX19wY2lfYXNzaWduX3Jlc291cmNl
KGJ1cywgZGV2LCByZXNubywgc2l6ZSwNCj4gbWluX2FsaWduKSkpIHsNCj4gPiA+PiArCXBoYiA9
IHBjaV9maW5kX2hvc3RfYnJpZGdlKGJ1cyk7DQo+ID4gPj4gKw0KPiA+ID4+ICsJaWYgKHBoYi0+
YWxpZ25fcmVzb3VyY2UpDQo+ID4gPj4gKwkJYWxpZ25mID0gcGhiLT5hbGlnbl9yZXNvdXJjZTsN
Cj4gPiA+PiArCWVsc2UNCj4gPiA+PiArCQlhbGlnbmYgPSBwY2liaW9zX2FsaWduX3Jlc291cmNl
Ow0KPiA+ID4+ICsNCj4gPiA+PiArCXdoaWxlICgocmV0ID0gX19wY2lfYXNzaWduX3Jlc291cmNl
KGJ1cywgZGV2LCByZXNubywgc2l6ZSwNCj4gPiA+PiArCQkJCQkgICAgbWluX2FsaWduLCBhbGln
bmYpKSkgew0KPiA+ID4+ICAJCWlmICghYnVzLT5wYXJlbnQgfHwgIWJ1cy0+c2VsZi0+dHJhbnNw
YXJlbnQpDQo+ID4gPj4gIAkJCWJyZWFrOw0KPiA+ID4+ICAJCWJ1cyA9IGJ1cy0+cGFyZW50Ow0K
PiA+ID4+IGRpZmYgLS1naXQgYS9pbmNsdWRlL2xpbnV4L3BjaS5oIGIvaW5jbHVkZS9saW51eC9w
Y2kuaA0KPiA+ID4+IGluZGV4IDM1M2RiOGQuLjM5ZTQ4ZmMgMTAwNjQ0DQo+ID4gPj4gLS0tIGEv
aW5jbHVkZS9saW51eC9wY2kuaA0KPiA+ID4+ICsrKyBiL2luY2x1ZGUvbGludXgvcGNpLmgNCj4g
PiA+PiBAQCAtNDA0LDYgKzQwNCw5IEBAIHN0cnVjdCBwY2lfaG9zdF9icmlkZ2Ugew0KPiA+ID4+
ICAJc3RydWN0IGRldmljZSBkZXY7DQo+ID4gPj4gIAlzdHJ1Y3QgcGNpX2J1cyAqYnVzOwkJLyog
cm9vdCBidXMgKi8NCj4gPiA+PiAgCXN0cnVjdCBsaXN0X2hlYWQgd2luZG93czsJLyogcmVzb3Vy
Y2VfZW50cnkgKi8NCj4gPiA+PiArCXJlc291cmNlX3NpemVfdCAoKmFsaWduX3Jlc291cmNlKSh2
b2lkICpkYXRhLA0KPiA+ID4+ICsJCQkgY29uc3Qgc3RydWN0IHJlc291cmNlICpyZXMsDQo+ID4g
Pj4gKwkJCSByZXNvdXJjZV9zaXplX3Qgc2l6ZSwgcmVzb3VyY2Vfc2l6ZV90IGFsaWduKTsNCj4g
PiA+PiAgCXZvaWQgKCpyZWxlYXNlX2ZuKShzdHJ1Y3QgcGNpX2hvc3RfYnJpZGdlICopOw0KPiA+
ID4+ICAJdm9pZCAqcmVsZWFzZV9kYXRhOw0KPiA+ID4+ICAJdW5zaWduZWQgaW50IGlnbm9yZV9y
ZXNldF9kZWxheToxOwkvKiBmb3IgZW50aXJlIGhpZXJhcmNoeQ0KPiAqLw0KPiA+ID4+IC0tDQo+
ID4gPj4gMS45LjENCj4gPiA+Pg0KPiA+ID4NCj4gPg0KPiA+DQo+ID4gLS0NCj4gPiBUbyB1bnN1
YnNjcmliZSBmcm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJzY3JpYmUgbGludXgt
cGNpIg0KPiBpbg0KPiA+IHRoZSBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpvcmRvbW9Admdlci5r
ZXJuZWwub3JnDQo+ID4gTW9yZSBtYWpvcmRvbW8gaW5mbyBhdCAgaHR0cDovL3ZnZXIua2VybmVs
Lm9yZy9tYWpvcmRvbW8taW5mby5odG1sDQo+ID4NCj4gDQo+IC0tDQo+ID09PT09PT09PT09PT09
PT09PT09DQo+IHwgSSB3b3VsZCBsaWtlIHRvIHwNCj4gfCBmaXggdGhlIHdvcmxkLCAgfA0KPiB8
IGJ1dCB0aGV5J3JlIG5vdCB8DQo+IHwgZ2l2aW5nIG1lIHRoZSAgIHwNCj4gIFwgc291cmNlIGNv
ZGUhICAvDQo+ICAgLS0tLS0tLS0tLS0tLS0tDQo+ICAgICDCr1xfKOODhClfL8KvDQo+IA0KPiAt
LQ0KPiBUbyB1bnN1YnNjcmliZSBmcm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJz
Y3JpYmUgbGludXgtcGNpIiBpbg0KPiB0aGUgYm9keSBvZiBhIG1lc3NhZ2UgdG8gbWFqb3Jkb21v
QHZnZXIua2VybmVsLm9yZw0KPiBNb3JlIG1ham9yZG9tbyBpbmZvIGF0ICBodHRwOi8vdmdlci5r
ZXJuZWwub3JnL21ham9yZG9tby1pbmZvLmh0bWwNCg==

Re: [PATCH v3 1/5] ARM/PCI: remove align_resource callback in pcibios_align_resource

[Zhou Wang]

On 2015/7/17 18:02, Gabriele Paoloni wrote:
> The following patch is maybe a better solution
> 
> Gab
>

Hi Gab,

Many thanks for your patch, I think this patch is cleaner than 1/4 in v2 patchset.
I will merge this one in my new series.

Thanks，
Zhou

> -----------------------
> This patch is needed in order to unify the PCIe designware
> framework for ARM and ARM64 architectures.
> In the PCIe designware unification process we are calling
> pci_create_root_bus() passing a "sysdata" parameter
> that is the same for both ARM and ARM64 and is of type
> "struct pcie_port*". In the ARM case this will cause
> a problem with the function pcibios_align_resource();
> in fact this will cast "dev->sysdata" to "struct pci_sys_data*",
> whereas designware had passed a "struct pcie_port*" pointer.
> 
> This patch solves the issue by removing "align_resource" from
> "pci_sys_data" struct and defining a static global function pointer
> in "bios32.c"
> 
> Signed-off-by: Gabriele Paoloni <gabriele.paoloni at huawei.com>
> ---
>  arch/arm/include/asm/mach/pci.h |  5 -----
>  arch/arm/kernel/bios32.c        | 12 ++++++++----
>  2 files changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
> index 28b9bb3..8a4e4de 100644
> --- a/arch/arm/include/asm/mach/pci.h
> +++ b/arch/arm/include/asm/mach/pci.h
> @@ -58,11 +58,6 @@ struct pci_sys_data {
>  					/* IRQ mapping				*/
>  	int		(*map_irq)(const struct pci_dev *, u8, u8);
>  					/* Resource alignement requirements	*/
> -	resource_size_t (*align_resource)(struct pci_dev *dev,
> -					  const struct resource *res,
> -					  resource_size_t start,
> -					  resource_size_t size,
> -					  resource_size_t align);
>  	void		*private_data;	/* platform controller private data	*/
>  };
>  
> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> index fcbbbb1..4cdc64d 100644
> --- a/arch/arm/kernel/bios32.c
> +++ b/arch/arm/kernel/bios32.c
> @@ -17,6 +17,11 @@
>  #include <asm/mach/pci.h>
>  
>  static int debug_pci;
> +static resource_size_t (*align_resource)(struct pci_dev *dev,
> +		  const struct resource *res,
> +		  resource_size_t start,
> +		  resource_size_t size,
> +		  resource_size_t align) = NULL;
>  
>  #ifdef CONFIG_PCI_MSI
>  struct msi_controller *pcibios_msi_controller(struct pci_dev *dev)
> @@ -468,7 +473,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
>  		sys->busnr   = busnr;
>  		sys->swizzle = hw->swizzle;
>  		sys->map_irq = hw->map_irq;
> -		sys->align_resource = hw->align_resource;
> +		align_resource = hw->align_resource;
>  		INIT_LIST_HEAD(&sys->resources);
>  
>  		if (hw->private_data)
> @@ -589,7 +594,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  				resource_size_t size, resource_size_t align)
>  {
>  	struct pci_dev *dev = data;
> -	struct pci_sys_data *sys = dev->sysdata;
>  	resource_size_t start = res->start;
>  
>  	if (res->flags & IORESOURCE_IO && start & 0x300)
> @@ -597,8 +601,8 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  
>  	start = (start + align - 1) & ~(align - 1);
>  
> -	if (sys->align_resource)
> -		return sys->align_resource(dev, res, start, size, align);
> +	if (align_resource)
> +		return align_resource(dev, res, start, size, align);
>  
>  	return start;
>  }
>