From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org, stable@vger.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Subject: [PATCH v3 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence
Date: Tue, 5 Nov 2019 11:48:12 +0900 [thread overview]
Message-ID: <1572922092-12323-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> (raw)
In-Reply-To: <1572922092-12323-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
According to the R-Car Gen2/3 manual, "Be sure to write the initial
value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT".
To avoid unexpected behaviors, this patch fixes it. Note that
the SPCHG bit of MACCTLR register description said "Only writing 1
is valid and writing 0 is invalid" but this "invalid" means
"ignored", not "prohibited". So, any documentation conflict doesn't
exist about writing the MACCTLR register.
Reported-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
Cc: <stable@vger.kernel.org> # v5.2+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/pcie-rcar.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
index 40d8c54..1bfec1f 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -91,8 +91,12 @@
#define LINK_SPEED_2_5GTS (1 << 16)
#define LINK_SPEED_5_0GTS (2 << 16)
#define MACCTLR 0x011058
+#define MACCTLR_RESERVED23_16 GENMASK(23, 16)
#define SPEED_CHANGE BIT(24)
#define SCRAMBLE_DISABLE BIT(27)
+#define LTSMDIS BIT(31)
+ /* Be sure to write the initial value (H'80FF 0000) to MACCTLR */
+#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_RESERVED23_16)
#define PMSR 0x01105c
#define MACS2R 0x011078
#define MACCGSPSETR 0x011084
@@ -613,6 +617,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
if (IS_ENABLED(CONFIG_PCI_MSI))
rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
+ rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
+
/* Finish initialization - establish a PCI Express link */
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
@@ -1235,6 +1241,7 @@ static int rcar_pcie_resume_noirq(struct device *dev)
return 0;
/* Re-establish the PCIe link */
+ rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
return rcar_pcie_wait_for_dl(pcie);
}
--
2.7.4
next prev parent reply other threads:[~2019-11-05 2:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 2:48 [PATCH v3 0/2] PCI: rcar: Fix missing MACCTLR register setting (take2) Yoshihiro Shimoda
2019-11-05 2:48 ` [PATCH v3 1/2] Revert "PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Yoshihiro Shimoda
2019-11-05 8:46 ` Geert Uytterhoeven
2019-11-05 2:48 ` Yoshihiro Shimoda [this message]
2019-11-05 8:50 ` [PATCH v3 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence Geert Uytterhoeven
2019-11-05 9:26 ` Yoshihiro Shimoda
2019-11-05 9:52 ` Geert Uytterhoeven
2019-11-05 10:11 ` Yoshihiro Shimoda
2019-11-05 10:26 ` Geert Uytterhoeven
2019-11-05 10:33 ` Yoshihiro Shimoda
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