From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>,
linux-pci <linux-pci@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
stable <stable@vger.kernel.org>
Subject: RE: [PATCH v3 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence
Date: Tue, 5 Nov 2019 09:26:39 +0000 [thread overview]
Message-ID: <TYAPR01MB45448947CB09B1A8AC1774A8D87E0@TYAPR01MB4544.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdWrQs49BFaN49odrG3k91d2rsRLPpCSvDcj5DhKeHPPaA@mail.gmail.com>
Hi Geert-san,
Thank you for your review!
> From: Geert Uytterhoeven, Sent: Tuesday, November 5, 2019 5:50 PM
>
> Hi Shimoda-san,
>
> On Tue, Nov 5, 2019 at 3:48 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > According to the R-Car Gen2/3 manual, "Be sure to write the initial
> > value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT".
> > To avoid unexpected behaviors, this patch fixes it. Note that
> > the SPCHG bit of MACCTLR register description said "Only writing 1
> > is valid and writing 0 is invalid" but this "invalid" means
> > "ignored", not "prohibited". So, any documentation conflict doesn't
> > exist about writing the MACCTLR register.
> >
> > Reported-by: Eugeniu Rosca <erosca@de.adit-jv.com>
> > Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
> > Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
> > Cc: <stable@vger.kernel.org> # v5.2+
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pci/controller/pcie-rcar.c
> > +++ b/drivers/pci/controller/pcie-rcar.c
> > @@ -91,8 +91,12 @@
> > #define LINK_SPEED_2_5GTS (1 << 16)
> > #define LINK_SPEED_5_0GTS (2 << 16)
> > #define MACCTLR 0x011058
> > +#define MACCTLR_RESERVED23_16 GENMASK(23, 16)
>
> MACCTLR_NFTS_MASK?
I should have said on previous email thread [1] though,
since SH7786 PCIE HW manual said NFTS (NFTS) but
any R-Car SoCs' HW manual said just Reserved with H'FF,
so that I prefer to describe RESERVED instead of NFTS.
Do you agree?
[1]
https://marc.info/?l=linux-renesas-soc&m=157242422327368&w=2
> > #define SPEED_CHANGE BIT(24)
> > #define SCRAMBLE_DISABLE BIT(27)
> > +#define LTSMDIS BIT(31)
> > + /* Be sure to write the initial value (H'80FF 0000) to MACCTLR */
>
> Do we need this comment?
It's a little redundant. So, I'll remove it.
> > +#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_RESERVED23_16)
> > #define PMSR 0x01105c
> > #define MACS2R 0x011078
> > #define MACCGSPSETR 0x011084
>
> With the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks!
Best regards,
Yoshihiro Shimoda
next prev parent reply other threads:[~2019-11-05 9:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 2:48 [PATCH v3 0/2] PCI: rcar: Fix missing MACCTLR register setting (take2) Yoshihiro Shimoda
2019-11-05 2:48 ` [PATCH v3 1/2] Revert "PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Yoshihiro Shimoda
2019-11-05 8:46 ` Geert Uytterhoeven
2019-11-05 2:48 ` [PATCH v3 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence Yoshihiro Shimoda
2019-11-05 8:50 ` Geert Uytterhoeven
2019-11-05 9:26 ` Yoshihiro Shimoda [this message]
2019-11-05 9:52 ` Geert Uytterhoeven
2019-11-05 10:11 ` Yoshihiro Shimoda
2019-11-05 10:26 ` Geert Uytterhoeven
2019-11-05 10:33 ` Yoshihiro Shimoda
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