From: Shawn Lin <shawn.lin@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
William Wu <william.wu@rock-chips.com>,
Simon Xue <xxm@rock-chips.com>,
linux-rockchip@lists.infradead.org,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller
Date: Tue, 14 Jan 2020 15:22:58 +0800 [thread overview]
Message-ID: <1578986580-71974-5-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1578986580-71974-1-git-send-email-shawn.lin@rock-chips.com>
From: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
.../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
new file mode 100644
index 0000000..c5205f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare based PCIe RC controller on Rockchip SoCs
+
+maintainers:
+ - Shawn Lin <shawn.lin@rock-chips.com>
+ - Simon Xue <xxm@rock-chips.com>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk1808-pcie
+ - snps,dw-pcie
+
+ reg:
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: High speed clock for PCIe
+ - description: Low speed clock for PCIe
+ - description: AHB clock for PCIe
+ - description: APB clock for PCIe
+ - description: Auxiliary clock for PCIe
+
+ clock-names:
+ items:
+ - const: hsclk
+ - const: lsclk
+ - const: aclk
+ - const: pclk
+ - const: sclk-aux
+
+ resets:
+ items:
+ - description: PCIe niu high reset line
+ - description: PCIe niu low reset line
+ - description: PCIe grf reset line
+ - description: PCIe control reset line
+ - description: PCIe control powerup reset line
+ - description: PCIe control master reset line
+ - description: PCIe control slave reset line
+ - description: PCIe control dbi reset line
+ - description: PCIe control button reset line
+ - description: PCIe control power engine reset line
+ - description: PCIe control core reset line
+ - description: PCIe control non-sticky reset line
+ - description: PCIe control sticky reset line
+ - description: PCIe control power reset line
+ - description: PCIe niu ahb reset line
+ - description: PCIe niu apb reset line
+
+ reset-names:
+ items:
+ - const: niu-h
+ - const: niu-l
+ - const: grf-p
+ - const: ctl-p
+ - const: ctl-powerup
+ - const: ctl-mst-a
+ - const: ctl-slv-a
+ - const: ctl-dbi-a
+ - const: ctl-button
+ - const: ctl-pe
+ - const: ctl-core
+ - const: ctl-nsticky
+ - const: ctl-sticky
+ - const: ctl-pwr
+ - const: ctl-niu-a
+ - const: ctl-niu-p
+
+ rockchip,usbpciegrf:
+ items:
+ - description: The grf for COMBPHY configuration and state registers.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - msi-map
+ - num-lanes
+ - phys
+ - phy-names
+ - resets
+ - reset-names
+ - rockchip,usbpciegrf
+
+additionalProperties: false
+
+examples:
+ - |
+ usb_pcie_grf: syscon@fe040000 {
+ compatible = "rockchip,usb-pcie-grf", "syscon";
+ reg = <0x0 0xfe040000 0x0 0x1000>;
+ };
+
+ pcie0: pcie@fc400000 {
+ compatible = "rockchip,rk1808-pcie", "snps,dw-pcie";
+ reg = <0x0 0xfc000000 0x0 0x400000>,
+ <0x0 0xfc400000 0x0 0x10000>;
+ clocks = <&cru HSCLK_PCIE>, <&cru LSCLK_PCIE>,
+ <&cru ACLK_PCIE>, <&cru PCLK_PCIE>,
+ <&cru SCLK_PCIE_AUX>;
+ clock-names = "hsclk", "lsclk",
+ "aclk", "pclk",
+ "sclk-aux";
+ msi-map = <0x0 &its 0x0 0x1000>;
+ num-lanes = <2>;
+ phys = <&combphy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ resets = <&cru SRST_PCIE_NIU_H>, <&cru SRST_PCIE_NIU_L>,
+ <&cru SRST_PCIEGRF_P>, <&cru SRST_PCIECTL_P>,
+ <&cru SRST_PCIECTL_POWERUP>, <&cru SRST_PCIECTL_MST_A>,
+ <&cru SRST_PCIECTL_SLV_A>, <&cru SRST_PCIECTL_DBI_A>,
+ <&cru SRST_PCIECTL_BUTTON>, <&cru SRST_PCIECTL_PE>,
+ <&cru SRST_PCIECTL_CORE>, <&cru SRST_PCIECTL_NSTICKY>,
+ <&cru SRST_PCIECTL_STICKY>, <&cru SRST_PCIECTL_PWR>,
+ <&cru SRST_PCIE_NIU_A>, <&cru SRST_PCIE_NIU_P>;
+ reset-names = "niu-h", "niu-l", "grf-p", "ctl-p",
+ "ctl-powerup", "ctl-mst-a", "ctl-slv-a",
+ "ctl-dbi-a", "ctl-button", "ctl-pe",
+ "ctl-core", "ctl-nsticky", "ctl-sticky",
+ "ctl-pwr", "ctl-niu-a", "ctl-niu-p";
+ rockchip,usbpciegrf = <&usb_pcie_grf>;
+ };
+
+...
--
1.9.1
next prev parent reply other threads:[~2020-01-14 7:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 7:22 [PATCH 0/6] Add Rockchip new PCIe controller and combo phy support Shawn Lin
2020-01-14 7:22 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Shawn Lin
2020-01-14 23:43 ` Rob Herring
2020-01-16 0:03 ` [PATCH 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP【请注意，邮件由linux-rockchip-bounces+shawn.lin=rock-chips.com@lists.infradead.org代发】 Shawn Lin
2020-01-14 7:22 ` [PATCH 2/6] phy/rockchip: inno-combophy: Add initial support Shawn Lin
2020-01-14 7:22 ` [PATCH 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Shawn Lin
2020-01-14 7:22 ` Shawn Lin [this message]
2020-01-15 0:05 ` [PATCH 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller Rob Herring
2020-01-14 7:25 ` [PATCH 5/6] PCI: rockchip: add " Shawn Lin
2020-01-15 17:24 ` Bjorn Helgaas
2020-01-16 0:14 ` Shawn Lin
2020-01-16 21:36 ` Jingoo Han
2020-01-18 16:36 ` Francesco Lavra
2020-01-20 0:55 ` Shawn Lin
2020-01-14 7:25 ` [PATCH 6/6] MAINTAINERS: Update PCIe drivers for Rockchip Shawn Lin
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