* [PATCH v2 1/6] PCI: add 32 GT/s decoding in some macros
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
2020-02-06 10:59 ` [PATCH v2 2/6] PCI: Add comments for link speed info arrays Yicong Yang
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Link speed 32.0 GT/s is supported in PCIe r5.0. Add in macro
PCIE_SPEED2STR and PCIE_SPEED2MBS_ENC to correctly decode.
This patch is a complementary to
commit de76cda215d5 ("PCI: Decode PCIe 32 GT/s link speed").
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/pci.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e6bcc06..d2e92b0f 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -296,7 +296,8 @@ void pci_bus_put(struct pci_bus *bus);
/* PCIe link information */
#define PCIE_SPEED2STR(speed) \
- ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
+ ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \
+ (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
(speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
(speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
(speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
@@ -304,7 +305,8 @@ void pci_bus_put(struct pci_bus *bus);
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
- ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
+ ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
+ (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
(speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/6] PCI: Add comments for link speed info arrays
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
2020-02-06 10:59 ` [PATCH v2 1/6] PCI: add 32 GT/s decoding in some macros Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
2020-02-06 10:59 ` [PATCH v2 3/6] PCI: Refactor and rename PCIE_SPEED2STR macro Yicong Yang
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Add comments for pcix_bus_speed[] and pcie_link_speed[] arrays.
Indicating the capabilities which the information from.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/probe.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 6ce47d8..84b012f 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -640,6 +640,10 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge)
}
EXPORT_SYMBOL(pci_free_host_bridge);
+/**
+ * these indices represent secondary bus mode and
+ * frequency from PCI_X_SSTATUS_FREQ
+ **/
static const unsigned char pcix_bus_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCI_SPEED_66MHz_PCIX, /* 1 */
@@ -659,6 +663,10 @@ static const unsigned char pcix_bus_speed[] = {
PCI_SPEED_133MHz_PCIX_533 /* F */
};
+/**
+ * these indices represent PCIe link speed from
+ * PCI_EXP_LNKCAP, PCI_EXP_LNKSTA, PCI_EXP_LNKCAP2
+ **/
const unsigned char pcie_link_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCIE_SPEED_2_5GT, /* 1 */
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/6] PCI: Refactor and rename PCIE_SPEED2STR macro
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
2020-02-06 10:59 ` [PATCH v2 1/6] PCI: add 32 GT/s decoding in some macros Yicong Yang
2020-02-06 10:59 ` [PATCH v2 2/6] PCI: Add comments for link speed info arrays Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
2020-02-06 10:59 ` [PATCH v2 4/6] PCI: Refactor bus_speed_read() with PCI_SPEED2STR macro Yicong Yang
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Use pci_bus_speed_strings[] array to refactor PCIE_SPEED2STR
macro. Rename it with PCI_SPEED2STR as it can also used to
decode non-PCIe speeds with pci_bus_speed_strings[].
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/pci-sysfs.c | 2 +-
drivers/pci/pci.c | 6 +++---
drivers/pci/pci.h | 10 +++-------
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 13f766d..f4eafbc 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -156,7 +156,7 @@ static ssize_t max_link_speed_show(struct device *dev,
{
struct pci_dev *pdev = to_pci_dev(dev);
- return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));
+ return sprintf(buf, "%s\n", PCI_SPEED2STR(pcie_get_speed_cap(pdev)));
}
static DEVICE_ATTR_RO(max_link_speed);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 3c30e72..7285fe0 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5871,14 +5871,14 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
if (bw_avail >= bw_cap && verbose)
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
bw_cap / 1000, bw_cap % 1000,
- PCIE_SPEED2STR(speed_cap), width_cap);
+ PCI_SPEED2STR(speed_cap), width_cap);
else if (bw_avail < bw_cap)
pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
bw_avail / 1000, bw_avail % 1000,
- PCIE_SPEED2STR(speed), width,
+ PCI_SPEED2STR(speed), width,
limiting_dev ? pci_name(limiting_dev) : "<unknown>",
bw_cap / 1000, bw_cap % 1000,
- PCIE_SPEED2STR(speed_cap), width_cap);
+ PCI_SPEED2STR(speed_cap), width_cap);
}
/**
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d2e92b0f..ba6b2cb 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -295,13 +295,9 @@ struct pci_bus *pci_bus_get(struct pci_bus *bus);
void pci_bus_put(struct pci_bus *bus);
/* PCIe link information */
-#define PCIE_SPEED2STR(speed) \
- ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \
- (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
- (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
- (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
- (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
- "Unknown speed")
+#define PCI_SPEED2STR(speed) \
+ ((speed) < pci_bus_speed_strings_size ? \
+ pci_bus_speed_strings[speed] : "Unknown speed")
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 4/6] PCI: Refactor bus_speed_read() with PCI_SPEED2STR macro
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
` (2 preceding siblings ...)
2020-02-06 10:59 ` [PATCH v2 3/6] PCI: Refactor and rename PCIE_SPEED2STR macro Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
2020-02-06 10:59 ` [PATCH v2 5/6] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro Yicong Yang
2020-02-06 10:59 ` [PATCH v2 6/6] PCI: Reduce redundancy in current_link_speed_show() Yicong Yang
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Use PCI_SPEED2STR macro to replace judgement statment in
bus_speed_read() function. Add "PCIe" suffix when decoding PCIe
speed for proper display.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/slot.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c
index fb7c172..871d598 100644
--- a/drivers/pci/slot.c
+++ b/drivers/pci/slot.c
@@ -51,14 +51,10 @@ static ssize_t address_read_file(struct pci_slot *slot, char *buf)
static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf)
{
- const char *speed_string;
+ if (speed <= PCI_SPEED_133MHz_PCIX_533)
+ return sprintf(buf, "%s\n", PCI_SPEED2STR(speed));
- if (speed < pci_bus_speed_strings_size)
- speed_string = pci_bus_speed_strings[speed];
- else
- speed_string = "Unknown";
-
- return sprintf(buf, "%s\n", speed_string);
+ return sprintf(buf, "%s PCIe\n", PCI_SPEED2STR(speed));
}
static ssize_t max_speed_read_file(struct pci_slot *slot, char *buf)
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 5/6] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
` (3 preceding siblings ...)
2020-02-06 10:59 ` [PATCH v2 4/6] PCI: Refactor bus_speed_read() with PCI_SPEED2STR macro Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
2020-02-06 10:59 ` [PATCH v2 6/6] PCI: Reduce redundancy in current_link_speed_show() Yicong Yang
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Add PCIE_LNKCAP2_SLS2SPEED macro for transforming raw link cap 2
value to link speed. Use it in pcie_get_speed_cap() to replace
judgement statements. Then we don't need to touch the functions
when new link speed comes.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/pci.c | 17 ++++-------------
drivers/pci/pci.h | 9 +++++++++
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7285fe0..99f34d5 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5783,19 +5783,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
* where only 2.5 GT/s and 5.0 GT/s speeds were defined.
*/
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
- if (lnkcap2) { /* PCIe r3.0-compliant */
- if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
- return PCIE_SPEED_32_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
- return PCIE_SPEED_16_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
- return PCIE_SPEED_8_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
- return PCIE_SPEED_5_0GT;
- else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
- return PCIE_SPEED_2_5GT;
- return PCI_SPEED_UNKNOWN;
- }
+
+ /* PCIe r3.0-compliant */
+ if (lnkcap2)
+ return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index ba6b2cb..7651749 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -299,6 +299,15 @@ void pci_bus_put(struct pci_bus *bus);
((speed) < pci_bus_speed_strings_size ? \
pci_bus_speed_strings[speed] : "Unknown speed")
+/* PCIe link information from Link Capabilities 2 */
+#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
+ ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
+ PCI_SPEED_UNKNOWN)
+
/* PCIe speed to Mb/s reduced by encoding overhead */
#define PCIE_SPEED2MBS_ENC(speed) \
((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 6/6] PCI: Reduce redundancy in current_link_speed_show()
2020-02-06 10:59 [PATCH v2 0/6] Improve link speed presentation process Yicong Yang
` (4 preceding siblings ...)
2020-02-06 10:59 ` [PATCH v2 5/6] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro Yicong Yang
@ 2020-02-06 10:59 ` Yicong Yang
5 siblings, 0 replies; 7+ messages in thread
From: Yicong Yang @ 2020-02-06 10:59 UTC (permalink / raw)
To: helgaas, linux-pci; +Cc: f.fangjian, huangdaode
Remove switch-case statements in current_link_speed_show(). Use
pcie_link_speed[] array to get link speed and PCI_SPEED2STR macro
to get link speed string.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/pci/pci-sysfs.c | 24 +++---------------------
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index f4eafbc..eaece10 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -175,33 +175,15 @@ static ssize_t current_link_speed_show(struct device *dev,
struct pci_dev *pci_dev = to_pci_dev(dev);
u16 linkstat;
int err;
- const char *speed;
+ enum pci_bus_speed speed;
err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);
if (err)
return -EINVAL;
- switch (linkstat & PCI_EXP_LNKSTA_CLS) {
- case PCI_EXP_LNKSTA_CLS_32_0GB:
- speed = "32 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_16_0GB:
- speed = "16 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_8_0GB:
- speed = "8 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_5_0GB:
- speed = "5 GT/s";
- break;
- case PCI_EXP_LNKSTA_CLS_2_5GB:
- speed = "2.5 GT/s";
- break;
- default:
- speed = "Unknown speed";
- }
+ speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];
- return sprintf(buf, "%s\n", speed);
+ return sprintf(buf, "%s\n", PCI_SPEED2STR(speed));
}
static DEVICE_ATTR_RO(current_link_speed);
--
2.8.1
^ permalink raw reply related [flat|nested] 7+ messages in thread