* [PATCH v3] PCI: dwc: Add upper limit address for outbound iATU
[not found] <CGME20210202072903epcas5p43dd06fede21ea3a31961b811507fb7f7@epcas5p4.samsung.com>
@ 2021-02-02 7:28 ` Shradha Todi
2021-02-04 10:01 ` Lorenzo Pieralisi
0 siblings, 1 reply; 2+ messages in thread
From: Shradha Todi @ 2021-02-02 7:28 UTC (permalink / raw)
To: linux-kernel, linux-pci
Cc: bhelgaas, robh, lorenzo.pieralisi, gustavo.pimentel, jingoohan1,
pankaj.dubey, sriram.dash, niyas.ahmed, p.rajanbabu, l.mehra,
hari.tv, Shradha Todi
The size parameter is unsigned long type which can accept size > 4GB. In
that case, the upper limit address must be programmed. Add support to
program the upper limit address and set INCREASE_REGION_SIZE in case size >
4GB.
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v1: https://lkml.org/lkml/2020/12/20/187
v2:
Addressed Rob's review comment and added PCI version check condition to
avoid writing to reserved registers.
v3:
Rebased on pci/dwc branch
drivers/pci/controller/dwc/pcie-designware.c | 5 +++++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index bfacdb3..dc23ece 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -332,11 +332,16 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
upper_32_bits(cpu_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
lower_32_bits(cpu_addr + size - 1));
+ if (pci->version >= 0x460A)
+ dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
+ upper_32_bits(cpu_addr + size - 1));
dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
lower_32_bits(pci_addr));
dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
upper_32_bits(pci_addr));
val = type | PCIE_ATU_FUNC_NUM(func_no);
+ val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
+ val | PCIE_ATU_INCREASE_REGION_SIZE : val;
if (pci->version == 0x490A)
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d8d2e0a..7247c8b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -100,6 +100,7 @@
#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_ATU_UPPER_LIMIT 0x924
#define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_DBI_RO_WR_EN BIT(0)
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v3] PCI: dwc: Add upper limit address for outbound iATU
2021-02-02 7:28 ` [PATCH v3] PCI: dwc: Add upper limit address for outbound iATU Shradha Todi
@ 2021-02-04 10:01 ` Lorenzo Pieralisi
0 siblings, 0 replies; 2+ messages in thread
From: Lorenzo Pieralisi @ 2021-02-04 10:01 UTC (permalink / raw)
To: Shradha Todi, linux-pci, linux-kernel
Cc: Lorenzo Pieralisi, gustavo.pimentel, niyas.ahmed, pankaj.dubey,
p.rajanbabu, jingoohan1, l.mehra, sriram.dash, robh, hari.tv,
bhelgaas
On Tue, 2 Feb 2021 12:58:38 +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
Applied to pci/dwc, thanks!
[1/1] PCI: dwc: Add upper limit address for outbound iATU
https://git.kernel.org/lpieralisi/pci/c/13662a07fd
Thanks,
Lorenzo
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2021-02-02 7:28 ` [PATCH v3] PCI: dwc: Add upper limit address for outbound iATU Shradha Todi
2021-02-04 10:01 ` Lorenzo Pieralisi
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