From: <bpeled@marvell.com>
To: <thomas.petazzoni@bootlin.com>, <lorenzo.pieralisi@arm.com>,
<bhelgaas@google.com>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<sebastian.hesselbarth@gmail.com>, <gregory.clement@bootlin.com>,
<andrew@lunn.ch>, <robh+dt@kernel.org>, <mw@semihalf.com>,
<jaz@semihalf.com>, <kostap@marvell.com>, <nadavh@marvell.com>,
<stefanc@marvell.com>, <oferh@marvell.com>,
Ben Peled <bpeled@marvell.com>,
Marc St-Amand <mstamand@ciena.com>
Subject: [”PATCH” v2 1/5] PCI: armada8k: Disable LTSSM on link down interrupts
Date: Wed, 14 Apr 2021 16:20:50 +0300 [thread overview]
Message-ID: <1618406454-7953-2-git-send-email-bpeled@marvell.com> (raw)
In-Reply-To: <1618406454-7953-1-git-send-email-bpeled@marvell.com>
From: Ben Peled <bpeled@marvell.com>
When a PCI link down condition is detected, the link training state
machine must be disabled immediately.
Signed-off-by: Marc St-Amand <mstamand@ciena.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Ben Peled <bpeled@marvell.com>
---
drivers/pci/controller/dwc/pcie-armada8k.c | 38 ++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index 13901f3..b2278b1 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -54,6 +54,10 @@ struct armada8k_pcie {
#define PCIE_INT_C_ASSERT_MASK BIT(11)
#define PCIE_INT_D_ASSERT_MASK BIT(12)
+#define PCIE_GLOBAL_INT_CAUSE2_REG (PCIE_VENDOR_REGS_OFFSET + 0x24)
+#define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28)
+#define PCIE_INT2_PHY_RST_LINK_DOWN BIT(1)
+
#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
@@ -193,6 +197,11 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
+ /* Also enable link down interrupts */
+ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG);
+ reg |= PCIE_INT2_PHY_RST_LINK_DOWN;
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, reg);
+
if (!dw_pcie_link_up(pci)) {
/* Configuration done. Start LTSSM */
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
@@ -230,6 +239,35 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG);
+
+ if (PCIE_INT2_PHY_RST_LINK_DOWN & val) {
+ u32 ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
+ /*
+ * The link went down. Disable LTSSM immediately. This
+ * unlocks the root complex config registers. Downstream
+ * device accesses will return all-Fs
+ */
+ ctrl_reg &= ~(PCIE_APP_LTSSM_EN);
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, ctrl_reg);
+ /*
+ * Mask link down interrupts. They can be re-enabled once
+ * the link is retrained.
+ */
+ ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG);
+ ctrl_reg &= ~PCIE_INT2_PHY_RST_LINK_DOWN;
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, ctrl_reg);
+ /*
+ * At this point a worker thread can be triggered to
+ * initiate a link retrain. If link retrains were
+ * possible, that is.
+ */
+ dev_dbg(pci->dev, "%s: link went down\n", __func__);
+ }
+
+ /* Now clear the second interrupt cause. */
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG, val);
+
return IRQ_HANDLED;
}
--
2.7.4
next prev parent reply other threads:[~2021-04-14 13:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 13:20 [”PATCH” v2 0/5] Asynchronous linkdown recovery bpeled
2021-04-14 13:20 ` bpeled [this message]
2021-12-09 11:28 ` [”PATCH” v2 1/5] PCI: armada8k: Disable LTSSM on link down interrupts Pali Rohár
2021-04-14 13:20 ` [”PATCH” v2 2/5] PCI: armada8k: Add link-down handle bpeled
2021-04-17 10:51 ` Pali Rohár
2021-04-14 13:20 ` [”PATCH” v2 3/5] dt-bindings: pci: add system controller and MAC reset bit to Armada 7K/8K controller bindings bpeled
2021-04-15 21:20 ` Rob Herring
2021-04-14 13:20 ` [”PATCH” v2 4/5] arm64: dts: marvell: add pcie mac reset to pcie bpeled
2021-04-14 13:20 ` [”PATCH” v2 5/5] PCI: armada8k: add device reset to link-down handle bpeled
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