From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-pci@vger.kernel.org, nvdimm@lists.linux.dev
Subject: [PATCH v3 06/40] cxl/acpi: Map component registers for Root Ports
Date: Sun, 23 Jan 2022 16:29:10 -0800 [thread overview]
Message-ID: <164298415080.3018233.14694957480228676592.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <164298411792.3018233.7493009997525360044.stgit@dwillia2-desk3.amr.corp.intel.com>
From: Ben Widawsky <ben.widawsky@intel.com>
This implements the TODO in cxl_acpi for mapping component registers.
cxl_acpi becomes the second consumer of CXL register block enumeration
(cxl_pci being the first). Moving the functionality to cxl_core allows
both of these drivers to use the functionality. Equally importantly it
allows cxl_core to use the functionality in the future.
CXL 2.0 root ports are similar to CXL 2.0 Downstream Ports with the main
distinction being they're a part of the CXL 2.0 host bridge. While
mapping their component registers is not immediately useful for the CXL
drivers, the movement of register block enumeration into core is a vital
step towards HDM decoder programming.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: fix cxl_regmap_to_base() failure cases]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/acpi.c | 13 +++++++++--
drivers/cxl/core/regs.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 4 +++
drivers/cxl/pci.c | 52 --------------------------------------------
drivers/cxl/pci.h | 9 ++++++++
5 files changed, 80 insertions(+), 54 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index 3163167ecc3a..c656a49a11a9 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -7,6 +7,7 @@
#include <linux/acpi.h>
#include <linux/pci.h>
#include "cxl.h"
+#include "pci.h"
/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways)
@@ -134,11 +135,13 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
__mock int match_add_root_ports(struct pci_dev *pdev, void *data)
{
+ resource_size_t creg = CXL_RESOURCE_NONE;
struct cxl_walk_context *ctx = data;
struct pci_bus *root_bus = ctx->root;
struct cxl_port *port = ctx->port;
int type = pci_pcie_type(pdev);
struct device *dev = ctx->dev;
+ struct cxl_register_map map;
u32 lnkcap, port_num;
int rc;
@@ -152,9 +155,15 @@ __mock int match_add_root_ports(struct pci_dev *pdev, void *data)
&lnkcap) != PCIBIOS_SUCCESSFUL)
return 0;
- /* TODO walk DVSEC to find component register base */
+ /* The driver doesn't rely on component registers for Root Ports yet. */
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ if (!rc)
+ dev_info(&pdev->dev, "No component register block found\n");
+
+ creg = cxl_regmap_to_base(pdev, &map);
+
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
- rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
+ rc = cxl_add_dport(port, &pdev->dev, port_num, creg);
if (rc) {
ctx->error = rc;
return rc;
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index e37e23bf4355..0d63758e2605 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -5,6 +5,7 @@
#include <linux/slab.h>
#include <linux/pci.h>
#include <cxlmem.h>
+#include <pci.h>
/**
* DOC: cxl registers
@@ -247,3 +248,58 @@ int cxl_map_device_regs(struct pci_dev *pdev,
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, CXL);
+
+static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
+ struct cxl_register_map *map)
+{
+ map->block_offset = ((u64)reg_hi << 32) |
+ (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK);
+ map->barno = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo);
+ map->reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo);
+}
+
+/**
+ * cxl_find_regblock() - Locate register blocks by type
+ * @pdev: The CXL PCI device to enumerate.
+ * @type: Register Block Indicator id
+ * @map: Enumeration output, clobbered on error
+ *
+ * Return: 0 if register block enumerated, negative error code otherwise
+ *
+ * A CXL DVSEC may point to one or more register blocks, search for them
+ * by @type.
+ */
+int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
+ struct cxl_register_map *map)
+{
+ u32 regloc_size, regblocks;
+ int regloc, i;
+
+ map->block_offset = U64_MAX;
+ regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
+ CXL_DVSEC_REG_LOCATOR);
+ if (!regloc)
+ return -ENXIO;
+
+ pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size);
+ regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size);
+
+ regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET;
+ regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8;
+
+ for (i = 0; i < regblocks; i++, regloc += 8) {
+ u32 reg_lo, reg_hi;
+
+ pci_read_config_dword(pdev, regloc, ®_lo);
+ pci_read_config_dword(pdev, regloc + 4, ®_hi);
+
+ cxl_decode_regblock(reg_lo, reg_hi, map);
+
+ if (map->reg_type == type)
+ return 0;
+ }
+
+ map->block_offset = U64_MAX;
+ return -ENODEV;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index a5a0be3f088b..6288a6c1fc5c 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -145,6 +145,10 @@ int cxl_map_device_regs(struct pci_dev *pdev,
struct cxl_device_regs *regs,
struct cxl_register_map *map);
+enum cxl_regloc_type;
+int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
+ struct cxl_register_map *map);
+
#define CXL_RESOURCE_NONE ((resource_size_t) -1)
#define CXL_TARGET_STRLEN 20
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 1eeba0ec46f3..bdfeb92ed028 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -367,58 +367,6 @@ static int cxl_map_regs(struct cxl_dev_state *cxlds, struct cxl_register_map *ma
return 0;
}
-static void cxl_decode_regblock(u32 reg_lo, u32 reg_hi,
- struct cxl_register_map *map)
-{
- map->block_offset = ((u64)reg_hi << 32) |
- (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK);
- map->barno = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo);
- map->reg_type = FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo);
-}
-
-/**
- * cxl_find_regblock() - Locate register blocks by type
- * @pdev: The CXL PCI device to enumerate.
- * @type: Register Block Indicator id
- * @map: Enumeration output, clobbered on error
- *
- * Return: 0 if register block enumerated, negative error code otherwise
- *
- * A CXL DVSEC may point to one or more register blocks, search for them
- * by @type.
- */
-static int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map)
-{
- u32 regloc_size, regblocks;
- int regloc, i;
-
- regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
- CXL_DVSEC_REG_LOCATOR);
- if (!regloc)
- return -ENXIO;
-
- pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size);
- regloc_size = FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size);
-
- regloc += CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET;
- regblocks = (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8;
-
- for (i = 0; i < regblocks; i++, regloc += 8) {
- u32 reg_lo, reg_hi;
-
- pci_read_config_dword(pdev, regloc, ®_lo);
- pci_read_config_dword(pdev, regloc + 4, ®_hi);
-
- cxl_decode_regblock(reg_lo, reg_hi, map);
-
- if (map->reg_type == type)
- return 0;
- }
-
- return -ENODEV;
-}
-
static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
struct cxl_register_map *map)
{
diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h
index 8ae2b4adc59d..0623bb85f30a 100644
--- a/drivers/cxl/pci.h
+++ b/drivers/cxl/pci.h
@@ -47,4 +47,13 @@ enum cxl_regloc_type {
CXL_REGLOC_RBI_TYPES
};
+static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
+ struct cxl_register_map *map)
+{
+ if (map->block_offset == U64_MAX)
+ return CXL_RESOURCE_NONE;
+
+ return pci_resource_start(pdev, map->barno) + map->block_offset;
+}
+
#endif /* __CXL_PCI_H__ */
next prev parent reply other threads:[~2022-01-24 0:29 UTC|newest]
Thread overview: 172+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 0:28 [PATCH v3 00/40] CXL.mem Topology Discovery and Hotplug Support Dan Williams
2022-01-24 0:28 ` [PATCH v3 01/40] cxl: Rename CXL_MEM to CXL_PCI Dan Williams
2022-01-24 0:28 ` [PATCH v3 02/40] cxl/pci: Implement Interface Ready Timeout Dan Williams
2022-01-31 22:21 ` Ben Widawsky
2022-01-31 23:11 ` Dan Williams
2022-01-31 23:25 ` Ben Widawsky
2022-01-31 23:47 ` Dan Williams
2022-01-31 23:51 ` [PATCH v4 " Dan Williams
2022-01-24 0:28 ` [PATCH v3 03/40] cxl/pci: Defer mailbox status checks to command timeouts Dan Williams
2022-01-31 22:28 ` Ben Widawsky
2022-01-24 0:29 ` [PATCH v3 04/40] cxl: Flesh out register names Dan Williams
2022-01-24 0:29 ` [PATCH v3 05/40] cxl/pci: Add new DVSEC definitions Dan Williams
2022-01-24 0:29 ` Dan Williams [this message]
2022-01-24 0:29 ` [PATCH v3 07/40] cxl: Introduce module_cxl_driver Dan Williams
2022-01-24 0:29 ` [PATCH v3 08/40] cxl/core/port: Rename bus.c to port.c Dan Williams
2022-01-31 22:34 ` Ben Widawsky
2022-01-24 0:29 ` [PATCH v3 09/40] cxl/decoder: Hide physical address information from non-root Dan Williams
2022-01-31 14:14 ` Jonathan Cameron
2022-01-31 22:34 ` Ben Widawsky
2022-01-24 0:29 ` [PATCH v3 10/40] cxl/core: Convert decoder range to resource Dan Williams
2022-01-24 0:29 ` [PATCH v3 11/40] cxl/core/port: Clarify decoder creation Dan Williams
2022-01-31 14:46 ` Jonathan Cameron
2022-01-31 21:17 ` Dan Williams
2022-01-31 21:33 ` [PATCH v4 " Dan Williams
2022-02-01 10:49 ` Jonathan Cameron
2022-01-24 0:29 ` [PATCH v3 12/40] cxl/core: Fix cxl_probe_component_regs() error message Dan Williams
2022-01-31 14:53 ` Jonathan Cameron
2022-01-31 22:29 ` Dan Williams
2022-01-31 22:39 ` Ben Widawsky
2022-01-24 0:29 ` [PATCH v3 13/40] cxl/core/port: Make passthrough decoder init implicit Dan Williams
2022-01-31 14:56 ` Jonathan Cameron
2022-01-24 0:29 ` [PATCH v3 14/40] cxl/core: Track port depth Dan Williams
2022-01-31 14:57 ` Jonathan Cameron
2022-01-24 0:29 ` [PATCH v3 15/40] cxl: Prove CXL locking Dan Williams
2022-01-31 15:48 ` Jonathan Cameron
2022-01-31 19:43 ` Dan Williams
2022-01-31 19:50 ` [PATCH v4 " Dan Williams
2022-01-31 23:23 ` Ben Widawsky
2022-01-24 0:30 ` [PATCH v3 16/40] cxl/core/port: Use dedicated lock for decoder target list Dan Williams
2022-01-26 2:54 ` [PATCH v4 " Dan Williams
2022-01-31 15:59 ` Jonathan Cameron
2022-01-31 23:31 ` Dan Williams
2022-01-31 23:34 ` Ben Widawsky
2022-01-31 23:38 ` Dan Williams
2022-01-31 23:42 ` Ben Widawsky
2022-01-31 23:58 ` Dan Williams
2022-01-31 23:35 ` [PATCH v5 " Dan Williams
2022-02-01 10:52 ` Jonathan Cameron
2022-01-24 0:30 ` [PATCH v3 17/40] cxl/port: Introduce cxl_port_to_pci_bus() Dan Williams
2022-01-31 16:04 ` Jonathan Cameron
2022-01-31 16:44 ` [PATCH v4 " Dan Williams
2022-01-31 23:41 ` Ben Widawsky
2022-01-24 0:30 ` [PATCH v3 18/40] cxl/pmem: Introduce a find_cxl_root() helper Dan Williams
2022-01-26 18:55 ` [PATCH v4 " Dan Williams
2022-01-26 23:59 ` [PATCH v5 " Dan Williams
2022-01-31 16:18 ` Jonathan Cameron
2022-02-01 0:22 ` Dan Williams
2022-02-01 10:58 ` Jonathan Cameron
2022-02-01 0:34 ` [PATCH v6 " Dan Williams
2022-02-01 10:59 ` Jonathan Cameron
2022-01-24 0:30 ` [PATCH v3 19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller Dan Williams
2022-01-31 16:20 ` Jonathan Cameron
2022-01-31 23:47 ` Ben Widawsky
2022-02-01 0:43 ` Dan Williams
2022-02-01 1:07 ` [PATCH v4 " Dan Williams
2022-02-01 11:00 ` Jonathan Cameron
2022-01-24 0:30 ` [PATCH v3 20/40] cxl/pci: Rename pci.h to cxlpci.h Dan Williams
2022-01-31 16:22 ` Jonathan Cameron
2022-02-01 0:00 ` Dan Williams
2022-01-31 23:48 ` Ben Widawsky
2022-01-24 0:30 ` [PATCH v3 21/40] cxl/core: Generalize dport enumeration in the core Dan Williams
2022-01-31 17:02 ` Jonathan Cameron
2022-02-01 1:58 ` Dan Williams
2022-02-01 2:10 ` [PATCH v4 " Dan Williams
2022-02-01 11:03 ` Jonathan Cameron
2022-01-24 0:30 ` [PATCH v3 22/40] cxl/core/hdm: Add CXL standard decoder enumeration to " Dan Williams
2022-01-26 3:09 ` [PATCH v4 " Dan Williams
2022-01-31 14:26 ` Jonathan Cameron
2022-01-31 17:51 ` Jonathan Cameron
2022-02-01 5:10 ` Dan Williams
2022-02-01 20:24 ` [PATCH v5 " Dan Williams
2022-02-02 9:31 ` Jonathan Cameron
2022-02-01 0:24 ` [PATCH v3 " Ben Widawsky
2022-02-01 4:58 ` Dan Williams
2022-01-24 0:30 ` [PATCH v3 23/40] cxl/core: Emit modalias for CXL devices Dan Williams
2022-01-31 17:57 ` Jonathan Cameron
2022-02-01 15:11 ` Ben Widawsky
2022-01-24 0:30 ` [PATCH v3 24/40] cxl/port: Add a driver for 'struct cxl_port' objects Dan Williams
2022-01-26 20:16 ` [PATCH v4 " Dan Williams
2022-01-31 18:11 ` Jonathan Cameron
2022-02-01 20:43 ` Dan Williams
2022-02-02 9:33 ` Jonathan Cameron
2022-02-01 21:07 ` [PATCH v5 " Dan Williams
2022-01-24 0:30 ` [PATCH v3 25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration Dan Williams
2022-01-31 14:32 ` Jonathan Cameron
2022-01-31 18:14 ` Jonathan Cameron
2022-02-01 15:17 ` Ben Widawsky
2022-02-01 21:09 ` Dan Williams
2022-02-01 21:23 ` [PATCH v4 " Dan Williams
2022-01-24 0:30 ` [PATCH v3 26/40] cxl/pci: Store component register base in cxlds Dan Williams
2022-01-31 18:15 ` Jonathan Cameron
2022-02-01 21:28 ` [PATCH v4 " Dan Williams
2022-01-24 0:31 ` [PATCH v3 27/40] cxl/pci: Cache device DVSEC offset Dan Williams
2022-01-31 18:19 ` Jonathan Cameron
2022-02-01 15:24 ` Ben Widawsky
2022-02-01 21:41 ` Dan Williams
2022-02-01 22:11 ` Ben Widawsky
2022-02-01 22:15 ` Dan Williams
2022-02-01 22:20 ` Ben Widawsky
2022-02-01 22:24 ` Dan Williams
2022-02-02 9:36 ` Jonathan Cameron
2022-02-01 22:06 ` [PATCH v4 " Dan Williams
2022-02-02 9:36 ` Jonathan Cameron
2022-01-24 0:31 ` [PATCH v3 28/40] cxl/pci: Retrieve CXL DVSEC memory info Dan Williams
2022-01-31 18:25 ` Jonathan Cameron
2022-02-01 22:52 ` Dan Williams
2022-02-01 23:48 ` [PATCH v4 " Dan Williams
2022-02-02 9:39 ` Jonathan Cameron
2022-01-24 0:31 ` [PATCH v3 29/40] cxl/pci: Implement wait for media active Dan Williams
2022-01-31 18:29 ` Jonathan Cameron
2022-02-01 23:56 ` Dan Williams
2022-01-24 0:31 ` [PATCH v3 30/40] cxl/pci: Emit device serial number Dan Williams
2022-01-31 18:33 ` Jonathan Cameron
2022-01-31 21:43 ` Dan Williams
2022-01-31 21:56 ` [PATCH v4 " Dan Williams
2022-01-24 0:31 ` [PATCH v3 31/40] cxl/memdev: Add numa_node attribute Dan Williams
2022-01-31 18:41 ` Jonathan Cameron
2022-02-01 23:57 ` Dan Williams
2022-02-02 9:44 ` Jonathan Cameron
2022-02-02 15:44 ` Dan Williams
2022-02-03 9:41 ` Jonathan Cameron
2022-02-03 16:59 ` Dan Williams
2022-02-03 18:05 ` Jonathan Cameron
2022-02-04 4:25 ` Dan Williams
2022-02-01 15:31 ` Ben Widawsky
2022-02-01 15:49 ` Jonathan Cameron
2022-02-01 16:35 ` Ben Widawsky
2022-02-01 17:38 ` Jonathan Cameron
2022-02-01 23:59 ` Dan Williams
2022-02-02 1:18 ` Dan Williams
2022-01-24 0:31 ` [PATCH v3 32/40] cxl/core/port: Add switch port enumeration Dan Williams
2022-02-01 12:13 ` Jonathan Cameron
2022-02-02 5:26 ` Dan Williams
2022-02-01 17:37 ` Ben Widawsky
2022-02-02 6:03 ` Dan Williams
2022-02-02 17:07 ` [PATCH v4 " Dan Williams
2022-02-03 9:55 ` Jonathan Cameron
2022-02-04 15:08 ` [PATCH v5 " Dan Williams
2022-01-24 0:31 ` [PATCH v3 33/40] cxl/mem: Add the cxl_mem driver Dan Williams
2022-01-26 3:16 ` [PATCH v4 " Dan Williams
2022-02-01 12:45 ` Jonathan Cameron
2022-02-01 17:44 ` Ben Widawsky
2022-02-03 2:49 ` Dan Williams
2022-02-03 9:59 ` Jonathan Cameron
2022-02-04 14:54 ` Dan Williams
2022-02-03 3:56 ` [PATCH v5 " Dan Williams
2022-02-03 12:07 ` Jonathan Cameron
2022-02-04 15:18 ` [PATCH v6 " Dan Williams
2022-01-24 0:31 ` [PATCH v3 34/40] cxl/core: Move target_list out of base decoder attributes Dan Williams
2022-01-31 18:45 ` Jonathan Cameron
2022-02-01 17:45 ` Ben Widawsky
2022-01-24 0:31 ` [PATCH v3 35/40] cxl/core/port: Add endpoint decoders Dan Williams
2022-02-01 12:47 ` Jonathan Cameron
2022-02-03 4:02 ` [PATCH v4 " Dan Williams
2022-02-14 17:45 ` Jonathan Cameron
2022-02-14 19:14 ` Dan Williams
2022-01-24 0:31 ` [PATCH v3 36/40] tools/testing/cxl: Mock dvsec_ranges() Dan Williams
2022-01-24 0:31 ` [PATCH v3 37/40] tools/testing/cxl: Fix root port to host bridge assignment Dan Williams
2022-01-24 0:32 ` [PATCH v3 38/40] tools/testing/cxl: Mock one level of switches Dan Williams
2022-01-24 0:32 ` [PATCH v3 39/40] tools/testing/cxl: Enumerate mock decoders Dan Williams
2022-01-24 0:32 ` [PATCH v3 40/40] tools/testing/cxl: Add a physical_node link Dan Williams
2022-02-01 12:53 ` Jonathan Cameron
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