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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<nvdimm@lists.linux.dev>
Subject: Re: [PATCH v3 25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration
Date: Mon, 31 Jan 2022 14:32:46 +0000	[thread overview]
Message-ID: <20220131143246.000047ab@Huawei.com> (raw)
In-Reply-To: <164298425201.3018233.647136583483232467.stgit@dwillia2-desk3.amr.corp.intel.com>

On Sun, 23 Jan 2022 16:30:52 -0800
Dan Williams <dan.j.williams@intel.com> wrote:

> Now that dport and decoder enumeration is centralized in the port
> driver, the @host argument for these helpers can be made implicit. For
> the root port the host is the port's uport device (ACPI0017 for
> cxl_acpi), and for all other descendant ports the devm context is the
> parent of @port.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Some minor docs follow through from earlier patches.

Jonathan

> ---
>  drivers/cxl/acpi.c            |    2 +-
>  drivers/cxl/core/hdm.c        |   10 +++++-----
>  drivers/cxl/core/pci.c        |    8 ++------
>  drivers/cxl/core/port.c       |    9 +++++++--
>  drivers/cxl/cxl.h             |    8 ++++----
>  drivers/cxl/cxlpci.h          |    2 +-
>  drivers/cxl/port.c            |    8 ++++----
>  tools/testing/cxl/test/cxl.c  |   14 +++++---------
>  tools/testing/cxl/test/mock.c |   28 ++++++++++++----------------
>  tools/testing/cxl/test/mock.h |    9 ++++-----
>  10 files changed, 45 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 82591642ea90..683f2ca32c97 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -256,7 +256,7 @@ static int add_host_bridge_dport(struct device *match, void *arg)
>  		return 0;
>  	}
>  
> -	dport = devm_cxl_add_dport(host, root_port, match, uid, ctx.chbcr);
> +	dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
>  	if (IS_ERR(dport)) {
>  		dev_err(host, "failed to add downstream port: %s\n",
>  			dev_name(match));
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 802048dc2046..701b510c76d2 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -44,7 +44,7 @@ static int add_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
>   * are claimed and passed to the single dport. Disable the range until the first
>   * CXL region is enumerated / activated.
>   */
> -int devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port)
> +int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
>  {
>  	struct cxl_decoder *cxld;
>  	struct cxl_dport *dport;
> @@ -96,18 +96,18 @@ static void __iomem *map_hdm_decoder_regs(struct cxl_port *port,
>   * devm_cxl_setup_hdm - map HDM decoder component registers
>   * @port: cxl_port to map
>   */
> -struct cxl_hdm *devm_cxl_setup_hdm(struct device *host, struct cxl_port *port)
> +struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port)

If it had been here earlier you'd now need to drop the docs for host.

>  {
>  	void __iomem *crb, __iomem *hdm;
>  	struct device *dev = &port->dev;
>  	struct cxl_hdm *cxlhdm;
>  
> -	cxlhdm = devm_kzalloc(host, sizeof(*cxlhdm), GFP_KERNEL);
> +	cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
>  	if (!cxlhdm)
>  		return ERR_PTR(-ENOMEM);
>  
>  	cxlhdm->port = port;
> -	crb = devm_cxl_iomap_block(host, port->component_reg_phys,
> +	crb = devm_cxl_iomap_block(dev, port->component_reg_phys,
>  				   CXL_COMPONENT_REG_BLOCK_SIZE);
>  	if (!crb) {
>  		dev_err(dev, "No component registers mapped\n");
> @@ -197,7 +197,7 @@ static void init_hdm_decoder(struct cxl_decoder *cxld, int *target_map,
>   * devm_cxl_enumerate_decoders - add decoder objects per HDM register set
>   * @port: cxl_port HDM capability to scan

Well that's not right.  

>   */
> -int devm_cxl_enumerate_decoders(struct device *host, struct cxl_hdm *cxlhdm)
> +int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
>  {
>  	void __iomem *hdm = cxlhdm->regs.hdm_decoder;
>  	struct cxl_port *port = cxlhdm->port;
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index a04220ebc03f..420296abc57a 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -15,7 +15,6 @@
>  
>  struct cxl_walk_context {
>  	struct pci_bus *bus;
> -	struct device *host;
>  	struct cxl_port *port;
>  	int type;
>  	int error;
> @@ -26,7 +25,6 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
>  {
>  	struct cxl_walk_context *ctx = data;
>  	struct cxl_port *port = ctx->port;
> -	struct device *host = ctx->host;
>  	struct pci_bus *bus = ctx->bus;
>  	int type = pci_pcie_type(pdev);
>  	struct cxl_register_map map;
> @@ -50,7 +48,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
>  		dev_dbg(&port->dev, "failed to find component registers\n");
>  
>  	port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
> -	dport = devm_cxl_add_dport(host, port, &pdev->dev, port_num,
> +	dport = devm_cxl_add_dport(port, &pdev->dev, port_num,
>  				   cxl_regmap_to_base(pdev, &map));
>  	if (IS_ERR(dport)) {
>  		ctx->error = PTR_ERR(dport);
> @@ -65,13 +63,12 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
>  
>  /**
>   * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
> - * @host: devm context
>   * @port: cxl_port whose ->uport is the upstream of dports to be enumerated
>   *
>   * Returns a positive number of dports enumerated or a negative error
>   * code.
>   */
> -int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port)
> +int devm_cxl_port_enumerate_dports(struct cxl_port *port)
>  {
>  	struct pci_bus *bus = cxl_port_to_pci_bus(port);
>  	struct cxl_walk_context ctx;
> @@ -86,7 +83,6 @@ int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port)
>  		type = PCI_EXP_TYPE_DOWNSTREAM;
>  
>  	ctx = (struct cxl_walk_context) {
> -		.host = host,
>  		.port = port,
>  		.bus = bus,
>  		.type = type,
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index efe66a8633a8..26c3eb9180cd 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -573,7 +573,6 @@ static void cxl_dport_unlink(void *data)
>  
>  /**
>   * devm_cxl_add_dport - append downstream port data to a cxl_port
> - * @host: devm context for allocations
>   * @port: the cxl_port that references this dport
>   * @dport_dev: firmware or PCI device representing the dport
>   * @port_id: identifier for this dport in a decoder's target list
> @@ -583,14 +582,20 @@ static void cxl_dport_unlink(void *data)
>   * either the port's host (for root ports), or the port itself (for
>   * switch ports)
>   */
> -struct cxl_dport *devm_cxl_add_dport(struct device *host, struct cxl_port *port,
> +struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
>  				     struct device *dport_dev, int port_id,
>  				     resource_size_t component_reg_phys)
>  {
>  	char link_name[CXL_TARGET_STRLEN];
>  	struct cxl_dport *dport;
> +	struct device *host;
>  	int rc;
>  
> +	if (is_cxl_root(port))
> +		host = port->uport;
> +	else
> +		host = &port->dev;
> +
>  	if (!host->driver) {
>  		dev_WARN_ONCE(&port->dev, 1, "dport:%s bad devm context\n",
>  			      dev_name(dport_dev));
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index cee71c6e2fed..7c714e559e95 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -307,7 +307,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  				   resource_size_t component_reg_phys,
>  				   struct cxl_port *parent_port);
>  struct cxl_port *find_cxl_root(struct device *dev);
> -struct cxl_dport *devm_cxl_add_dport(struct device *host, struct cxl_port *port,
> +struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
>  				     struct device *dport, int port_id,
>  				     resource_size_t component_reg_phys);
>  struct cxl_decoder *to_cxl_decoder(struct device *dev);
> @@ -321,9 +321,9 @@ int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
>  int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
>  int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
>  struct cxl_hdm;
> -struct cxl_hdm *devm_cxl_setup_hdm(struct device *host, struct cxl_port *port);
> -int devm_cxl_enumerate_decoders(struct device *host, struct cxl_hdm *cxlhdm);
> -int devm_cxl_add_passthrough_decoder(struct device *host, struct cxl_port *port);
> +struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port);
> +int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm);
> +int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
>  
>  extern struct bus_type cxl_bus_type;
>  
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 47640f19e899..766de340c4ce 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -58,5 +58,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
>  	return pci_resource_start(pdev, map->barno) + map->block_offset;
>  }
>  
> -int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port);
> +int devm_cxl_port_enumerate_dports(struct cxl_port *port);
>  #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 7b42f27c0c96..ae94a537eccc 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -31,18 +31,18 @@ static int cxl_port_probe(struct device *dev)
>  	struct cxl_hdm *cxlhdm;
>  	int rc;
>  
> -	rc = devm_cxl_port_enumerate_dports(dev, port);
> +	rc = devm_cxl_port_enumerate_dports(port);
>  	if (rc < 0)
>  		return rc;
>  
>  	if (rc == 1)
> -		return devm_cxl_add_passthrough_decoder(dev, port);
> +		return devm_cxl_add_passthrough_decoder(port);
>  
> -	cxlhdm = devm_cxl_setup_hdm(dev, port);
> +	cxlhdm = devm_cxl_setup_hdm(port);
>  	if (IS_ERR(cxlhdm))
>  		return PTR_ERR(cxlhdm);
>  
> -	rc = devm_cxl_enumerate_decoders(dev, cxlhdm);
> +	rc = devm_cxl_enumerate_decoders(cxlhdm);
>  	if (rc) {
>  		dev_err(&port->dev, "Couldn't enumerate decoders (%d)\n", rc);
>  		return rc;
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index ce6ace286fc7..40ed567952e6 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -399,8 +399,7 @@ static struct acpi_pci_root *mock_acpi_pci_find_root(acpi_handle handle)
>  	return &mock_pci_root[host_bridge_index(adev)];
>  }
>  
> -static struct cxl_hdm *mock_cxl_setup_hdm(struct device *host,
> -					  struct cxl_port *port)
> +static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port)
>  {
>  	struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
>  
> @@ -411,21 +410,18 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct device *host,
>  	return cxlhdm;
>  }
>  
> -static int mock_cxl_add_passthrough_decoder(struct device *host,
> -					    struct cxl_port *port)
> +static int mock_cxl_add_passthrough_decoder(struct cxl_port *port)
>  {
>  	dev_err(&port->dev, "unexpected passthrough decoder for cxl_test\n");
>  	return -EOPNOTSUPP;
>  }
>  
> -static int mock_cxl_enumerate_decoders(struct device *host,
> -				       struct cxl_hdm *cxlhdm)
> +static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
>  {
>  	return 0;
>  }
>  
> -static int mock_cxl_port_enumerate_dports(struct device *host,
> -					  struct cxl_port *port)
> +static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
>  {
>  	struct device *dev = &port->dev;
>  	int i;
> @@ -437,7 +433,7 @@ static int mock_cxl_port_enumerate_dports(struct device *host,
>  		if (pdev->dev.parent != port->uport)
>  			continue;
>  
> -		dport = devm_cxl_add_dport(host, port, &pdev->dev, pdev->id,
> +		dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
>  					   CXL_RESOURCE_NONE);
>  
>  		if (IS_ERR(dport)) {
> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
> index 18d3b65e2a9b..6e8c9d63c92d 100644
> --- a/tools/testing/cxl/test/mock.c
> +++ b/tools/testing/cxl/test/mock.c
> @@ -131,66 +131,62 @@ __wrap_nvdimm_bus_register(struct device *dev,
>  }
>  EXPORT_SYMBOL_GPL(__wrap_nvdimm_bus_register);
>  
> -struct cxl_hdm *__wrap_devm_cxl_setup_hdm(struct device *host,
> -					  struct cxl_port *port)
> +struct cxl_hdm *__wrap_devm_cxl_setup_hdm(struct cxl_port *port)
>  {
>  	int index;
>  	struct cxl_hdm *cxlhdm;
>  	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>  
>  	if (ops && ops->is_mock_port(port->uport))
> -		cxlhdm = ops->devm_cxl_setup_hdm(host, port);
> +		cxlhdm = ops->devm_cxl_setup_hdm(port);
>  	else
> -		cxlhdm = devm_cxl_setup_hdm(host, port);
> +		cxlhdm = devm_cxl_setup_hdm(port);
>  	put_cxl_mock_ops(index);
>  
>  	return cxlhdm;
>  }
>  EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_setup_hdm, CXL);
>  
> -int __wrap_devm_cxl_add_passthrough_decoder(struct device *host,
> -					    struct cxl_port *port)
> +int __wrap_devm_cxl_add_passthrough_decoder(struct cxl_port *port)
>  {
>  	int rc, index;
>  	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>  
>  	if (ops && ops->is_mock_port(port->uport))
> -		rc = ops->devm_cxl_add_passthrough_decoder(host, port);
> +		rc = ops->devm_cxl_add_passthrough_decoder(port);
>  	else
> -		rc = devm_cxl_add_passthrough_decoder(host, port);
> +		rc = devm_cxl_add_passthrough_decoder(port);
>  	put_cxl_mock_ops(index);
>  
>  	return rc;
>  }
>  EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_passthrough_decoder, CXL);
>  
> -int __wrap_devm_cxl_enumerate_decoders(struct device *host,
> -				       struct cxl_hdm *cxlhdm)
> +int __wrap_devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm)
>  {
>  	int rc, index;
>  	struct cxl_port *port = cxlhdm->port;
>  	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>  
>  	if (ops && ops->is_mock_port(port->uport))
> -		rc = ops->devm_cxl_enumerate_decoders(host, cxlhdm);
> +		rc = ops->devm_cxl_enumerate_decoders(cxlhdm);
>  	else
> -		rc = devm_cxl_enumerate_decoders(host, cxlhdm);
> +		rc = devm_cxl_enumerate_decoders(cxlhdm);
>  	put_cxl_mock_ops(index);
>  
>  	return rc;
>  }
>  EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_enumerate_decoders, CXL);
>  
> -int __wrap_devm_cxl_port_enumerate_dports(struct device *host,
> -					  struct cxl_port *port)
> +int __wrap_devm_cxl_port_enumerate_dports(struct cxl_port *port)
>  {
>  	int rc, index;
>  	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>  
>  	if (ops && ops->is_mock_port(port->uport))
> -		rc = ops->devm_cxl_port_enumerate_dports(host, port);
> +		rc = ops->devm_cxl_port_enumerate_dports(port);
>  	else
> -		rc = devm_cxl_port_enumerate_dports(host, port);
> +		rc = devm_cxl_port_enumerate_dports(port);
>  	put_cxl_mock_ops(index);
>  
>  	return rc;
> diff --git a/tools/testing/cxl/test/mock.h b/tools/testing/cxl/test/mock.h
> index 15e48063ea4b..738f24e3988a 100644
> --- a/tools/testing/cxl/test/mock.h
> +++ b/tools/testing/cxl/test/mock.h
> @@ -19,11 +19,10 @@ struct cxl_mock_ops {
>  	bool (*is_mock_bus)(struct pci_bus *bus);
>  	bool (*is_mock_port)(struct device *dev);
>  	bool (*is_mock_dev)(struct device *dev);
> -	int (*devm_cxl_port_enumerate_dports)(struct device *host,
> -					      struct cxl_port *port);
> -	struct cxl_hdm *(*devm_cxl_setup_hdm)(struct device *host, struct cxl_port *port);
> -	int (*devm_cxl_add_passthrough_decoder)(struct device *host, struct cxl_port *port);
> -	int (*devm_cxl_enumerate_decoders)(struct device *host, struct cxl_hdm *hdm);
> +	int (*devm_cxl_port_enumerate_dports)(struct cxl_port *port);
> +	struct cxl_hdm *(*devm_cxl_setup_hdm)(struct cxl_port *port);
> +	int (*devm_cxl_add_passthrough_decoder)(struct cxl_port *port);
> +	int (*devm_cxl_enumerate_decoders)(struct cxl_hdm *hdm);
>  };
>  
>  void register_cxl_mock_ops(struct cxl_mock_ops *ops);
> 


  reply	other threads:[~2022-01-31 14:32 UTC|newest]

Thread overview: 172+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-24  0:28 [PATCH v3 00/40] CXL.mem Topology Discovery and Hotplug Support Dan Williams
2022-01-24  0:28 ` [PATCH v3 01/40] cxl: Rename CXL_MEM to CXL_PCI Dan Williams
2022-01-24  0:28 ` [PATCH v3 02/40] cxl/pci: Implement Interface Ready Timeout Dan Williams
2022-01-31 22:21   ` Ben Widawsky
2022-01-31 23:11     ` Dan Williams
2022-01-31 23:25       ` Ben Widawsky
2022-01-31 23:47         ` Dan Williams
2022-01-31 23:51   ` [PATCH v4 " Dan Williams
2022-01-24  0:28 ` [PATCH v3 03/40] cxl/pci: Defer mailbox status checks to command timeouts Dan Williams
2022-01-31 22:28   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 04/40] cxl: Flesh out register names Dan Williams
2022-01-24  0:29 ` [PATCH v3 05/40] cxl/pci: Add new DVSEC definitions Dan Williams
2022-01-24  0:29 ` [PATCH v3 06/40] cxl/acpi: Map component registers for Root Ports Dan Williams
2022-01-24  0:29 ` [PATCH v3 07/40] cxl: Introduce module_cxl_driver Dan Williams
2022-01-24  0:29 ` [PATCH v3 08/40] cxl/core/port: Rename bus.c to port.c Dan Williams
2022-01-31 22:34   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 09/40] cxl/decoder: Hide physical address information from non-root Dan Williams
2022-01-31 14:14   ` Jonathan Cameron
2022-01-31 22:34   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 10/40] cxl/core: Convert decoder range to resource Dan Williams
2022-01-24  0:29 ` [PATCH v3 11/40] cxl/core/port: Clarify decoder creation Dan Williams
2022-01-31 14:46   ` Jonathan Cameron
2022-01-31 21:17     ` Dan Williams
2022-01-31 21:33   ` [PATCH v4 " Dan Williams
2022-02-01 10:49     ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 12/40] cxl/core: Fix cxl_probe_component_regs() error message Dan Williams
2022-01-31 14:53   ` Jonathan Cameron
2022-01-31 22:29     ` Dan Williams
2022-01-31 22:39   ` Ben Widawsky
2022-01-24  0:29 ` [PATCH v3 13/40] cxl/core/port: Make passthrough decoder init implicit Dan Williams
2022-01-31 14:56   ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 14/40] cxl/core: Track port depth Dan Williams
2022-01-31 14:57   ` Jonathan Cameron
2022-01-24  0:29 ` [PATCH v3 15/40] cxl: Prove CXL locking Dan Williams
2022-01-31 15:48   ` Jonathan Cameron
2022-01-31 19:43     ` Dan Williams
2022-01-31 19:50   ` [PATCH v4 " Dan Williams
2022-01-31 23:23     ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 16/40] cxl/core/port: Use dedicated lock for decoder target list Dan Williams
2022-01-26  2:54   ` [PATCH v4 " Dan Williams
2022-01-31 15:59     ` Jonathan Cameron
2022-01-31 23:31       ` Dan Williams
2022-01-31 23:34     ` Ben Widawsky
2022-01-31 23:38       ` Dan Williams
2022-01-31 23:42         ` Ben Widawsky
2022-01-31 23:58           ` Dan Williams
2022-01-31 23:35     ` [PATCH v5 " Dan Williams
2022-02-01 10:52       ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 17/40] cxl/port: Introduce cxl_port_to_pci_bus() Dan Williams
2022-01-31 16:04   ` Jonathan Cameron
2022-01-31 16:44   ` [PATCH v4 " Dan Williams
2022-01-31 23:41     ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 18/40] cxl/pmem: Introduce a find_cxl_root() helper Dan Williams
2022-01-26 18:55   ` [PATCH v4 " Dan Williams
2022-01-26 23:59     ` [PATCH v5 " Dan Williams
2022-01-31 16:18       ` Jonathan Cameron
2022-02-01  0:22         ` Dan Williams
2022-02-01 10:58           ` Jonathan Cameron
2022-02-01  0:34       ` [PATCH v6 " Dan Williams
2022-02-01 10:59         ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller Dan Williams
2022-01-31 16:20   ` Jonathan Cameron
2022-01-31 23:47   ` Ben Widawsky
2022-02-01  0:43     ` Dan Williams
2022-02-01  1:07   ` [PATCH v4 " Dan Williams
2022-02-01 11:00     ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 20/40] cxl/pci: Rename pci.h to cxlpci.h Dan Williams
2022-01-31 16:22   ` Jonathan Cameron
2022-02-01  0:00     ` Dan Williams
2022-01-31 23:48   ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 21/40] cxl/core: Generalize dport enumeration in the core Dan Williams
2022-01-31 17:02   ` Jonathan Cameron
2022-02-01  1:58     ` Dan Williams
2022-02-01  2:10   ` [PATCH v4 " Dan Williams
2022-02-01 11:03     ` Jonathan Cameron
2022-01-24  0:30 ` [PATCH v3 22/40] cxl/core/hdm: Add CXL standard decoder enumeration to " Dan Williams
2022-01-26  3:09   ` [PATCH v4 " Dan Williams
2022-01-31 14:26     ` Jonathan Cameron
2022-01-31 17:51     ` Jonathan Cameron
2022-02-01  5:10       ` Dan Williams
2022-02-01 20:24     ` [PATCH v5 " Dan Williams
2022-02-02  9:31       ` Jonathan Cameron
2022-02-01  0:24   ` [PATCH v3 " Ben Widawsky
2022-02-01  4:58     ` Dan Williams
2022-01-24  0:30 ` [PATCH v3 23/40] cxl/core: Emit modalias for CXL devices Dan Williams
2022-01-31 17:57   ` Jonathan Cameron
2022-02-01 15:11   ` Ben Widawsky
2022-01-24  0:30 ` [PATCH v3 24/40] cxl/port: Add a driver for 'struct cxl_port' objects Dan Williams
2022-01-26 20:16   ` [PATCH v4 " Dan Williams
2022-01-31 18:11     ` Jonathan Cameron
2022-02-01 20:43       ` Dan Williams
2022-02-02  9:33         ` Jonathan Cameron
2022-02-01 21:07     ` [PATCH v5 " Dan Williams
2022-01-24  0:30 ` [PATCH v3 25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration Dan Williams
2022-01-31 14:32   ` Jonathan Cameron [this message]
2022-01-31 18:14   ` Jonathan Cameron
2022-02-01 15:17   ` Ben Widawsky
2022-02-01 21:09     ` Dan Williams
2022-02-01 21:23   ` [PATCH v4 " Dan Williams
2022-01-24  0:30 ` [PATCH v3 26/40] cxl/pci: Store component register base in cxlds Dan Williams
2022-01-31 18:15   ` Jonathan Cameron
2022-02-01 21:28   ` [PATCH v4 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 27/40] cxl/pci: Cache device DVSEC offset Dan Williams
2022-01-31 18:19   ` Jonathan Cameron
2022-02-01 15:24     ` Ben Widawsky
2022-02-01 21:41       ` Dan Williams
2022-02-01 22:11         ` Ben Widawsky
2022-02-01 22:15           ` Dan Williams
2022-02-01 22:20             ` Ben Widawsky
2022-02-01 22:24               ` Dan Williams
2022-02-02  9:36                 ` Jonathan Cameron
2022-02-01 22:06   ` [PATCH v4 " Dan Williams
2022-02-02  9:36     ` Jonathan Cameron
2022-01-24  0:31 ` [PATCH v3 28/40] cxl/pci: Retrieve CXL DVSEC memory info Dan Williams
2022-01-31 18:25   ` Jonathan Cameron
2022-02-01 22:52     ` Dan Williams
2022-02-01 23:48   ` [PATCH v4 " Dan Williams
2022-02-02  9:39     ` Jonathan Cameron
2022-01-24  0:31 ` [PATCH v3 29/40] cxl/pci: Implement wait for media active Dan Williams
2022-01-31 18:29   ` Jonathan Cameron
2022-02-01 23:56     ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 30/40] cxl/pci: Emit device serial number Dan Williams
2022-01-31 18:33   ` Jonathan Cameron
2022-01-31 21:43     ` Dan Williams
2022-01-31 21:56   ` [PATCH v4 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 31/40] cxl/memdev: Add numa_node attribute Dan Williams
2022-01-31 18:41   ` Jonathan Cameron
2022-02-01 23:57     ` Dan Williams
2022-02-02  9:44       ` Jonathan Cameron
2022-02-02 15:44         ` Dan Williams
2022-02-03  9:41           ` Jonathan Cameron
2022-02-03 16:59             ` Dan Williams
2022-02-03 18:05               ` Jonathan Cameron
2022-02-04  4:25                 ` Dan Williams
2022-02-01 15:31   ` Ben Widawsky
2022-02-01 15:49     ` Jonathan Cameron
2022-02-01 16:35       ` Ben Widawsky
2022-02-01 17:38         ` Jonathan Cameron
2022-02-01 23:59     ` Dan Williams
2022-02-02  1:18     ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 32/40] cxl/core/port: Add switch port enumeration Dan Williams
2022-02-01 12:13   ` Jonathan Cameron
2022-02-02  5:26     ` Dan Williams
2022-02-01 17:37   ` Ben Widawsky
2022-02-02  6:03     ` Dan Williams
2022-02-02 17:07   ` [PATCH v4 " Dan Williams
2022-02-03  9:55     ` Jonathan Cameron
2022-02-04 15:08     ` [PATCH v5 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 33/40] cxl/mem: Add the cxl_mem driver Dan Williams
2022-01-26  3:16   ` [PATCH v4 " Dan Williams
2022-02-01 12:45     ` Jonathan Cameron
2022-02-01 17:44       ` Ben Widawsky
2022-02-03  2:49       ` Dan Williams
2022-02-03  9:59         ` Jonathan Cameron
2022-02-04 14:54           ` Dan Williams
2022-02-03  3:56     ` [PATCH v5 " Dan Williams
2022-02-03 12:07       ` Jonathan Cameron
2022-02-04 15:18       ` [PATCH v6 " Dan Williams
2022-01-24  0:31 ` [PATCH v3 34/40] cxl/core: Move target_list out of base decoder attributes Dan Williams
2022-01-31 18:45   ` Jonathan Cameron
2022-02-01 17:45   ` Ben Widawsky
2022-01-24  0:31 ` [PATCH v3 35/40] cxl/core/port: Add endpoint decoders Dan Williams
2022-02-01 12:47   ` Jonathan Cameron
2022-02-03  4:02   ` [PATCH v4 " Dan Williams
2022-02-14 17:45     ` Jonathan Cameron
2022-02-14 19:14       ` Dan Williams
2022-01-24  0:31 ` [PATCH v3 36/40] tools/testing/cxl: Mock dvsec_ranges() Dan Williams
2022-01-24  0:31 ` [PATCH v3 37/40] tools/testing/cxl: Fix root port to host bridge assignment Dan Williams
2022-01-24  0:32 ` [PATCH v3 38/40] tools/testing/cxl: Mock one level of switches Dan Williams
2022-01-24  0:32 ` [PATCH v3 39/40] tools/testing/cxl: Enumerate mock decoders Dan Williams
2022-01-24  0:32 ` [PATCH v3 40/40] tools/testing/cxl: Add a physical_node link Dan Williams
2022-02-01 12:53   ` Jonathan Cameron

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