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* [PATCH v3] PCI: cadence: Allow PTM Responder to be enabled
@ 2022-05-12  5:55 Christian Gmeiner
  2022-05-12 14:41 ` Lorenzo Pieralisi
  0 siblings, 1 reply; 2+ messages in thread
From: Christian Gmeiner @ 2022-05-12  5:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: dominic.rath, kishon, Christian Gmeiner, Tom Joseph,
	Lorenzo Pieralisi, Rob Herring, Krzysztof Wilczyński,
	Bjorn Helgaas, linux-pci

This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bits are both set.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
 drivers/pci/controller/cadence/pcie-cadence.h      |  4 ++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index fb96d37a135c..940c7dd701d6 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
 	return ret;
 }
 
+static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
+{
+	u32 val;
+
+	val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
+	cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
+}
+
 static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
 {
 	struct cdns_pcie *pcie = &rc->pcie;
@@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	if (rc->quirk_detect_quiet_flag)
 		cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
 
+	cdns_pcie_host_enable_ptm_response(pcie);
+
 	ret = cdns_pcie_start_link(pcie);
 	if (ret) {
 		dev_err(dev, "Failed to start link\n");
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index c8a27b6290ce..1ffa8fa77a8a 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -116,6 +116,10 @@
 #define LM_RC_BAR_CFG_APERTURE(bar, aperture)		\
 					(((aperture) - 2) << ((bar) * 8))
 
+/* PTM Control Register */
+#define CDNS_PCIE_LM_PTM_CTRL 	(CDNS_PCIE_LM_BASE + 0x0da8)
+#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN 	BIT(17)
+
 /*
  * Endpoint Function Registers (PCI configuration space for endpoint functions)
  */
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH v3] PCI: cadence: Allow PTM Responder to be enabled
  2022-05-12  5:55 [PATCH v3] PCI: cadence: Allow PTM Responder to be enabled Christian Gmeiner
@ 2022-05-12 14:41 ` Lorenzo Pieralisi
  0 siblings, 0 replies; 2+ messages in thread
From: Lorenzo Pieralisi @ 2022-05-12 14:41 UTC (permalink / raw)
  To: Christian Gmeiner, linux-kernel
  Cc: Lorenzo Pieralisi, kishon, dominic.rath, Bjorn Helgaas,
	Rob Herring, Tom Joseph, linux-pci, Krzysztof Wilczyński

On Thu, 12 May 2022 07:55:38 +0200, Christian Gmeiner wrote:
> This enables the Controller [RP] to automatically respond with
> Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> and PCI_PTM_CTRL_ENABLE bits are both set.
> 
> 

Applied to pci/cadence, thanks!

[1/1] PCI: cadence: Allow PTM Responder to be enabled
      https://git.kernel.org/lpieralisi/pci/c/0f0cd520aa

Thanks,
Lorenzo

^ permalink raw reply	[flat|nested] 2+ messages in thread

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