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From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, bhelgaas@google.com,
	lorenzo.pieralisi@arm.com, festevam@gmail.com
Cc: hongxing.zhu@nxp.com, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: [RFC 1/2] PCI: imx6: Make sure the DBI register can be changed
Date: Wed, 18 May 2022 17:35:27 +0800	[thread overview]
Message-ID: <1652866528-13220-1-git-send-email-hongxing.zhu@nxp.com> (raw)

The PCIE_DBI_RO_WR_EN bit should be set when write some DBI registers.
To make sure that the DBI registers are writable, set the
PCIE_DBI_RO_WR_EN properly when touch the DBI registers.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6619e3caffe2..30641d2dda14 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -797,10 +797,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
 	 * started in Gen2 mode, there is a possibility the devices on the
 	 * bus will not be detected at all.  This happens with PCIe switches.
 	 */
+	dw_pcie_dbi_ro_wr_en(pci);
 	tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 	tmp &= ~PCI_EXP_LNKCAP_SLS;
 	tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
 	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	/* Start LTSSM. */
 	imx6_pcie_ltssm_enable(dev);
@@ -809,6 +811,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
 
 	if (pci->link_gen == 2) {
 		/* Allow Gen2 mode after the link is up. */
+		dw_pcie_dbi_ro_wr_en(pci);
 		tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 		tmp &= ~PCI_EXP_LNKCAP_SLS;
 		tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
@@ -821,6 +824,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
 		tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 		tmp |= PORT_LOGIC_SPEED_CHANGE;
 		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
+		dw_pcie_dbi_ro_wr_dis(pci);
 
 		if (imx6_pcie->drvdata->flags &
 		    IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
-- 
2.25.1


             reply	other threads:[~2022-05-18  9:48 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-18  9:35 Richard Zhu [this message]
2022-05-18  9:35 ` [RFC 2/2] PCI: imx6: Support more than Gen2 speed link mode Richard Zhu
2022-07-20  0:59   ` Tim Harvey
2022-07-20  1:43     ` Hongxing Zhu
2022-07-20  3:07       ` Hongxing Zhu
2022-07-11 22:17 ` [RFC 1/2] PCI: imx6: Make sure the DBI register can be changed Bjorn Helgaas
2022-07-12  1:30   ` Hongxing Zhu
2022-07-12 19:26     ` Bjorn Helgaas

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