From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
To: helgaas@kernel.org
Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com,
quic_hemantk@quicinc.com, quic_ramkri@quicinc.com,
manivannan.sadhasivam@linaro.org, swboyd@chromium.org,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>
Subject: [PATCH v1] PCI: qcom: Allow L1 and its sub states on qcom dwc wrapper
Date: Fri, 3 Jun 2022 12:48:50 +0530 [thread overview]
Message-ID: <1654240730-31322-1-git-send-email-quic_krichai@quicinc.com> (raw)
Allow L1 and its sub-states in the qcom dwc pcie wrapper.
By default its disabled. So enable it explicitly.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 6ab9089..f60645c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -41,6 +41,9 @@
#define L23_CLK_RMV_DIS BIT(2)
#define L1_CLK_RMV_DIS BIT(1)
+#define PCIE20_PARF_PM_CTRL 0x20
+#define REQ_NOT_ENTR_L1 BIT(5)
+
#define PCIE20_PARF_PHY_CTRL 0x40
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
@@ -1267,6 +1270,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
val |= BIT(4);
writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+ /* Clear PARF PM REQ_NOT_ENTR_L1 bit to allow L1 states */
+ val = readl(pcie->parf + PCIE20_PARF_PM_CTRL);
+ val &= ~REQ_NOT_ENTR_L1;
+ writel(val, pcie->parf + PCIE20_PARF_PM_CTRL);
+
if (IS_ENABLED(CONFIG_PCI_MSI)) {
val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
val |= BIT(31);
--
2.7.4
next reply other threads:[~2022-06-03 7:20 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-03 7:18 Krishna chaitanya chundru [this message]
2022-06-08 22:17 ` [PATCH v1] PCI: qcom: Allow L1 and its sub states on qcom dwc wrapper Stephen Boyd
2022-06-15 13:14 ` Krishna Chaitanya Chundru
2022-06-15 15:44 ` Bjorn Helgaas
2022-06-09 11:26 ` Manivannan Sadhasivam
2022-06-15 13:14 ` Krishna Chaitanya Chundru
2022-06-15 13:15 ` [PATCH v2] PCI: qcom: Allow L1 and its sub states Krishna chaitanya chundru
2022-06-24 8:02 ` Krishna Chaitanya Chundru
2022-06-24 9:02 ` Manivannan Sadhasivam
2022-06-24 17:11 ` Bjorn Helgaas
2022-07-15 8:24 ` Manivannan Sadhasivam
2022-07-15 11:29 ` Krishna Chaitanya Chundru
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