From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
To: helgaas@kernel.org
Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com,
quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com,
quic_skananth@quicinc.com, quic_ramkri@quicinc.com,
manivannan.sadhasivam@linaro.org, swboyd@chromium.org,
"Prasad Malisetty" <quic_pmaliset@quicinc.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Saheed O. Bolarinwa" <refactormyself@gmail.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rajat Jain" <rajatja@google.com>
Subject: [PATCH v4] PCI/ASPM: Update LTR threshold based upon reported max latencies
Date: Fri, 3 Jun 2022 13:24:19 +0530 [thread overview]
Message-ID: <1654242861-15695-1-git-send-email-quic_krichai@quicinc.com> (raw)
In-Reply-To: <1646679549-12494-1-git-send-email-quic_pmaliset@quicinc.com>
From: Prasad Malisetty <quic_pmaliset@quicinc.com>
In ASPM driver, LTR threshold scale and value are updated based on
tcommon_mode and t_poweron values. In kioxia NVMe L1.2 is failing due to
LTR threshold scale and value are greater values than max snoop/non-snoop
value.
Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when
reported snoop/no-snoop values is greather than or equal to
LTR_L1.2_THRESHOLD value.
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
I am taking this patch forward as prasad is no more working with our org.
changes since v3:
- Changed the logic to include this condition "snoop/nosnoop
latencies are not equal to zero and lower than LTR_L1.2_THRESHOLD"
Changes since v2:
- Replaced LTRME logic with max snoop/no-snoop latencies check.
Changes since v1:
- Added missing variable declaration in v1 patch
---
drivers/pci/pcie/aspm.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index a96b742..c8f6253 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -461,14 +461,36 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
{
struct pci_dev *child = link->downstream, *parent = link->pdev;
u32 val1, val2, scale1, scale2;
+ u32 max_val, max_scale, max_snp_scale, max_snp_val, max_nsnp_scale, max_nsnp_val;
u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
u32 ctl1 = 0, ctl2 = 0;
u32 pctl1, pctl2, cctl1, cctl2;
u32 pl1_2_enables, cl1_2_enables;
+ u16 ltr;
+ u16 max_snoop_lat, max_nosnoop_lat;
if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
return;
+ ltr = pci_find_ext_capability(child, PCI_EXT_CAP_ID_LTR);
+ if (!ltr)
+ return;
+
+ pci_read_config_word(child, ltr + PCI_LTR_MAX_SNOOP_LAT, &max_snoop_lat);
+ pci_read_config_word(child, ltr + PCI_LTR_MAX_NOSNOOP_LAT, &max_nosnoop_lat);
+
+ max_snp_scale = (max_snoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT;
+ max_snp_val = (max_snoop_lat & PCI_LTR_VALUE_MASK);
+
+ max_nsnp_scale = (max_nosnoop_lat & PCI_LTR_SCALE_MASK) >> PCI_LTR_SCALE_SHIFT;
+ max_nsnp_val = (max_nosnoop_lat & PCI_LTR_VALUE_MASK);
+
+ /* choose the greater max scale value between snoop and no snoop value*/
+ max_scale = (max_snp_scale > max_nsnp_scale) ? max_snp_scale: max_nsnp_scale;
+
+ /* choose the greater max value between snoop and no snoop scales */
+ max_val = (max_snp_val > max_nsnp_val) ? max_snp_val: max_nsnp_val;
+
/* Choose the greater of the two Port Common_Mode_Restore_Times */
val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
@@ -501,6 +523,16 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
*/
l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
encode_l12_threshold(l1_2_threshold, &scale, &value);
+
+ /*
+ * Based on PCIe r4.1, sec 5.5.1, L1.2 substate must be entered when reported
+ * snoop/no-snoop values are greather than or equal to LTR_L1.2_THRESHOLD value.
+ */
+ if (scale > max_scale)
+ scale = max_scale;
+ if (value > max_val)
+ value = max_val;
+
ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
/* Some broken devices only support dword access to L1 SS */
--
2.7.4
next prev parent reply other threads:[~2022-06-03 7:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 18:59 [PATCH v2] [RFC PATCH] PCI: Update LTR threshold based on LTRME bit Prasad Malisetty
2022-03-17 19:07 ` Stephen Boyd
2022-04-05 6:24 ` Prasad Malisetty (Temp)
2022-04-05 18:57 ` Stephen Boyd
2022-04-05 16:08 ` Bjorn Helgaas
2022-04-12 22:46 ` Bjorn Helgaas
2022-06-01 12:23 ` [PATCH v3] PCI/ASPM: Update LTR threshold based upon reported max latencies Krishna chaitanya chundru
2022-06-01 12:27 ` Krishna Chaitanya Chundru
2022-06-02 8:29 ` Manivannan Sadhasivam
2022-06-02 9:59 ` Krishna Chaitanya Chundru
2022-06-03 7:54 ` Krishna chaitanya chundru [this message]
2022-06-08 22:22 ` [PATCH v4] " Stephen Boyd
2022-06-10 5:08 ` [PATCH v5] " Krishna chaitanya chundru
2022-06-15 13:23 ` Krishna Chaitanya Chundru
2022-07-15 8:28 ` Manivannan Sadhasivam
2022-07-15 11:28 ` Krishna Chaitanya Chundru
2022-06-15 17:39 ` Manivannan Sadhasivam
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