RE: [PATCH v2] [RFC PATCH] PCI: Update LTR threshold based on LTRME bit

["Prasad Malisetty (Temp)" <pmaliset@qti.qualcomm.com>]

Hi Stephen, 

Thanks for the review and comments. Please find my comments inline below.

Thanks
-Prasad

> -----Original Message-----
> From: Stephen Boyd <swboyd@chromium.org>
> Sent: Friday, March 18, 2022 12:37 AM
> To: Prasad Malisetty (Temp) (QUIC) <quic_pmaliset@quicinc.com>;
> agross@kernel.org; bhelgaas@google.com; bjorn.andersson@linaro.org;
> kw@linux.com; linux-arm-msm@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-pci@vger.kernel.org; lorenzo.pieralisi@arm.com; rajatja@google.com;
> refactormyself@gmail.com; robh@kernel.org
> Cc: Veerabhadrarao Badiganti (QUIC) <quic_vbadigan@quicinc.com>; Rama
> Krishna (QUIC) <quic_ramkri@quicinc.com>;
> manivannan.sadhasivam@linaro.org
> Subject: Re: [PATCH v2] [RFC PATCH] PCI: Update LTR threshold based on
> LTRME bit
> 
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> 
> Quoting Prasad Malisetty (2022-03-07 10:59:09)
> > Update LTR threshold scale and value based on LTRME (Latency
> > Tolenrance Reporting Mechanism) from device capabilities.
> >
> > In ASPM driver, LTR threshold scale and value is updating based on
> > tcommon_mode and t_poweron values. In kioxia NVMe,
> > L1.2 is failing due to LTR threshold scale and value is greater values
> > than max snoop/non snoop value.
> >
> > In general, updated LTR threshold scale and value should be less than
> > max snoop/non snoop value to enter the device into L1.2 state.
> >
> > Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
> >
> 
> Any Fixes tag?
No, we don’t have any fixes tag as this is new issue identified in kioxia NVMe only as of now.
> 
> > ---
> > Changes since v1:
> >         - Added missing variable declaration in v1 patch.
> > ---
> >  drivers/pci/pcie/aspm.c | 12 +++++++++---
> >  1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index
> > a96b742..a67746c 100644
> > --- a/drivers/pci/pcie/aspm.c
> > +++ b/drivers/pci/pcie/aspm.c
> > @@ -463,6 +463,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state
> *link,
> >         u32 val1, val2, scale1, scale2;
> >         u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
> >         u32 ctl1 = 0, ctl2 = 0;
> > +       u32 cap;
> >         u32 pctl1, pctl2, cctl1, cctl2;
> >         u32 pl1_2_enables, cl1_2_enables;
> >
> > @@ -499,9 +500,14 @@ static void aspm_calc_l1ss_info(struct
> pcie_link_state *link,
> >          * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
> >          * least 4us.
> 
> Can this comment be updated to include why LTR cap matters?

Sure, I will update the comment in next patch version. 
> 
> >          */
> > -       l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
> > -       encode_l12_threshold(l1_2_threshold, &scale, &value);
> > -       ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
> > +       pcie_capability_read_dword(child, PCI_EXP_DEVCAP2, &cap);
> > +       if (!(cap & PCI_EXP_DEVCAP2_LTR)) {
> > +               l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
> > +               encode_l12_threshold(l1_2_threshold, &scale, &value);
> > +               ctl1 |= scale << 29 | value << 16;
> > +       }
> > +
> > +       ctl1 |= t_common_mode;