[PATCH v3 0/6] Add the iMX8MP PCIe support

[PATCH v3 0/6] Add the iMX8MP PCIe support

[Richard Zhu]

Based on the 6.0-rc1 of the pci/next branch. 
This series adds the i.MX8MP PCIe support and had been tested on i.MX8MP
EVK board when one PCIe NVME device is used.

- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
  Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
  And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
  driver.

Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
  external OSC is used as PCIe referrence clock. It's true. Remove all
  the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
  with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.

Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
  and linux-phy@lists.infradead.org.
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 +++++++--
arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46 ++++++++++++++++++++++++-
drivers/pci/controller/dwc/pci-imx6.c                        |  17 +++++++++-
drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
drivers/reset/reset-imx7.c                                   |   1 +
6 files changed, 232 insertions(+), 51 deletions(-)

 [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
 [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
 [PATCH v3 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
 [PATCH v3 4/6] arm64: dts: imx8mp: add the iMX8MP PCIe support
 [PATCH v3 5/6] arm64: dts: imx8mp-evk: Add PCIe support
 [PATCH v3 6/6] PCI: imx6: Add the iMX8MP PCIe support

[PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

[Richard Zhu]

On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
of SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.

And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add the i.MX8MP PCIe PHY PERST support here.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/reset/reset-imx7.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
 		break;
 
 	case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+	case IMX8MP_RESET_PCIEPHY_PERST:
 		value = assert ? 0 : bit;
 		break;
 	}
-- 
2.25.1

Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

[Philipp Zabel]

Hi Richard,

On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
> of SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> 
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So add the i.MX8MP PCIe PHY PERST support here.

the description is good now. It would be nice if this could also be
mentioned in the Reference Manual.

Please replace "add" with "fix" in the subject, as I requested earlier:
"reset: imx7: Fix i.MX8MP PCIe PHY PERST support".

And add a fixes line:

Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")

With those two changes,
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

RE: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

[Hongxing Zhu]

> -----Original Message-----
> From: Philipp Zabel <p.zabel@pengutronix.de>
> Sent: 2022年8月18日 16:51
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> support
> 
> Hi Richard,
> 
> On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> >
> > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > So add the i.MX8MP PCIe PHY PERST support here.
> 
> the description is good now. It would be nice if this could also be mentioned in
> the Reference Manual.
> 
> Please replace "add" with "fix" in the subject, as I requested earlier:
> "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> 
> And add a fixes line:
> 
> Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> 
> With those two changes,
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> 
Hi Philipp:
Okay, would be changed in next version.
Thanks for your review.

Best Regards
Richard Zhu

> regards
> Philipp

Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

[Lorenzo Pieralisi]

On Thu, Aug 18, 2022 at 10:53:24AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Philipp Zabel <p.zabel@pengutronix.de>
> > Sent: 2022年8月18日 16:51
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> > marex@denx.de
> > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > <linux-imx@nxp.com>
> > Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> > support
> > 
> > Hi Richard,
> > 
> > On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> > >
> > > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > > So add the i.MX8MP PCIe PHY PERST support here.
> > 
> > the description is good now. It would be nice if this could also be mentioned in
> > the Reference Manual.
> > 
> > Please replace "add" with "fix" in the subject, as I requested earlier:
> > "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> > 
> > And add a fixes line:
> > 
> > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > 
> > With those two changes,
> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> > 
> Hi Philipp:
> Okay, would be changed in next version.

AFAICS there is still a pending comment on patch (2) but I will
mark this as "Changes requested" and wait for the next version.

Lorenzo

> Thanks for your review.
> 
> Best Regards
> Richard Zhu
> 
> > regards
> > Philipp
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support

[Hongxing Zhu]

> -----Original Message-----
> From: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Sent: 2022年8月29日 16:10
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Philipp Zabel <p.zabel@pengutronix.de>; l.stach@pengutronix.de;
> bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com;
> marex@denx.de; linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST
> support
> 
> On Thu, Aug 18, 2022 at 10:53:24AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Philipp Zabel <p.zabel@pengutronix.de>
> > > Sent: 2022年8月18日 16:51
> > > To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> > > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org;
> > > shawnguo@kernel.org; vkoul@kernel.org;
> > > alexander.stein@ew.tq-group.com; marex@denx.de
> > > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > > <linux-imx@nxp.com>
> > > Subject: Re: [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY
> > > PERST support
> > >
> > > Hi Richard,
> > >
> > > On Do, 2022-08-18 at 15:02 +0800, Richard Zhu wrote:
> > > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > > > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> > > >
> > > > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > > > So add the i.MX8MP PCIe PHY PERST support here.
> > >
> > > the description is good now. It would be nice if this could also be
> > > mentioned in the Reference Manual.
> > >
> > > Please replace "add" with "fix" in the subject, as I requested earlier:
> > > "reset: imx7: Fix i.MX8MP PCIe PHY PERST support".
> > >
> > > And add a fixes line:
> > >
> > > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > >
> > > With those two changes,
> > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> > >
> > Hi Philipp:
> > Okay, would be changed in next version.
> 
> AFAICS there is still a pending comment on patch (2) but I will mark this as
> "Changes requested" and wait for the next version.
> 
Hi Lorenzo:
Thanks for your kindly help.
I had prepared the v4 version. And I also pinged Lucas privately and hope
 he can take a look at it. Thus, I can add his ack in v4 series.

Anyway, I would issue the v4 series tomorrow.
Best Regards
Richard Zhu

> Lorenzo
> 
> > Thanks for your review.
> >
> > Best Regards
> > Richard Zhu
> >
> > > regards
> > > Philipp
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=05%7
> C0
> >
> 1%7Chongxing.zhu%40nxp.com%7Cd0470ce757e64e6e7c6a08da8995e689%
> 7C686ea1
> >
> d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637973574166682920%7CUnk
> nown%7CTW
> >
> FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV
> CI6
> >
> Mn0%3D%7C3000%7C%7C%7C&amp;sdata=LE4i5OQ03XV0tUo%2FWIm8L9m
> Nx7ZNZMUhfpo
> > Lji4%2BDRM%3D&amp;reserved=0

[PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

[Richard Zhu]

Add i.MX8MP PCIe PHY binding.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     enum:
       - fsl,imx8mm-pcie-phy
+      - fsl,imx8mp-pcie-phy
 
   reg:
     maxItems: 1
@@ -28,11 +29,16 @@ properties:
       - const: ref
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   reset-names:
-    items:
-      - const: pciephy
+    oneOf:
+      - items:          # for iMX8MM
+          - const: pciephy
+      - items:          # for IMX8MP
+          - const: pciephy
+          - const: perst
 
   fsl,refclk-pad-mode:
     description: |
@@ -60,6 +66,10 @@ properties:
     description: A boolean property indicating the CLKREQ# signal is
       not supported in the board design (optional)
 
+  power-domains:
+    description: PCIe PHY  power domain (optional).
+    maxItems: 1
+
 required:
   - "#phy-cells"
   - compatible
-- 
2.25.1

Re: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

[Rob Herring]

On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY binding.

Explain the differences in h/w. The phy is connected to PERST#?

> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> index b6421eedece3..692783c7fd69 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> @@ -16,6 +16,7 @@ properties:
>    compatible:
>      enum:
>        - fsl,imx8mm-pcie-phy
> +      - fsl,imx8mp-pcie-phy
>  
>    reg:
>      maxItems: 1
> @@ -28,11 +29,16 @@ properties:
>        - const: ref
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
>  
>    reset-names:
> -    items:
> -      - const: pciephy
> +    oneOf:
> +      - items:          # for iMX8MM
> +          - const: pciephy
> +      - items:          # for IMX8MP
> +          - const: pciephy
> +          - const: perst

This does the same thing:

minItems: 1
items:
  - const: pciephy
  - const: perst


>  
>    fsl,refclk-pad-mode:
>      description: |
> @@ -60,6 +66,10 @@ properties:
>      description: A boolean property indicating the CLKREQ# signal is
>        not supported in the board design (optional)
>  
> +  power-domains:
> +    description: PCIe PHY  power domain (optional).
> +    maxItems: 1
> +
>  required:
>    - "#phy-cells"
>    - compatible
> -- 
> 2.25.1
> 
> 

RE: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

[Hongxing Zhu]

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2022年8月23日 2:07
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; shawnguo@kernel.org; vkoul@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
> 
> On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY binding.
> 
> Explain the differences in h/w. The phy is connected to PERST#?
> 
Hi Rob:
Thanks for your review comments.
Yes, it is. PERST# impacts PCIe PHY too.
The default value of this bit is 1b'1 on i.MX8MQ/i.MX8MM platforms. 
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
The PERST bit should be kept 1b'1 after power and clocks are stable.
So add the PHY PERST explicitly for i.MX8MP PCIe PHY.

> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > index b6421eedece3..692783c7fd69 100644
> > --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > @@ -16,6 +16,7 @@ properties:
> >    compatible:
> >      enum:
> >        - fsl,imx8mm-pcie-phy
> > +      - fsl,imx8mp-pcie-phy
> >
> >    reg:
> >      maxItems: 1
> > @@ -28,11 +29,16 @@ properties:
> >        - const: ref
> >
> >    resets:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> >
> >    reset-names:
> > -    items:
> > -      - const: pciephy
> > +    oneOf:
> > +      - items:          # for iMX8MM
> > +          - const: pciephy
> > +      - items:          # for IMX8MP
> > +          - const: pciephy
> > +          - const: perst
> 
> This does the same thing:
> 
> minItems: 1
> items:
>   - const: pciephy
>   - const: perst
> 
Okay, thanks.

Best Regards
Richard Zhu
> 
> >
> >    fsl,refclk-pad-mode:
> >      description: |
> > @@ -60,6 +66,10 @@ properties:
> >      description: A boolean property indicating the CLKREQ# signal is
> >        not supported in the board design (optional)
> >
> > +  power-domains:
> > +    description: PCIe PHY  power domain (optional).
> > +    maxItems: 1
> > +
> >  required:
> >    - "#phy-cells"
> >    - compatible
> > --
> > 2.25.1
> >
> >

RE: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding

[Hongxing Zhu]

> -----Original Message-----
> From: Hongxing Zhu
> Sent: 2022年8月23日 10:12
> To: Rob Herring <robh@kernel.org>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; shawnguo@kernel.org; vkoul@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: RE: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
> 
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: 2022年8月23日 2:07
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de;
> > bhelgaas@google.com; lorenzo.pieralisi@arm.com; shawnguo@kernel.org;
> > vkoul@kernel.org; alexander.stein@ew.tq-group.com; marex@denx.de;
> > linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> > <linux-imx@nxp.com>
> > Subject: Re: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY
> > binding
> >
> > On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
> > > Add i.MX8MP PCIe PHY binding.
> >
> > Explain the differences in h/w. The phy is connected to PERST#?
> >
> Hi Rob:
> Thanks for your review comments.
> Yes, it is. PERST# impacts PCIe PHY too.
> The default value of this bit is 1b'1 on i.MX8MQ/i.MX8MM platforms.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> The PERST bit should be kept 1b'1 after power and clocks are stable.
> So add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> 
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > ---
> > >  .../bindings/phy/fsl,imx8-pcie-phy.yaml          | 16
> +++++++++++++---
> > >  1 file changed, 13 insertions(+), 3 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > > index b6421eedece3..692783c7fd69 100644
> > > --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > > @@ -16,6 +16,7 @@ properties:
> > >    compatible:
> > >      enum:
> > >        - fsl,imx8mm-pcie-phy
> > > +      - fsl,imx8mp-pcie-phy
> > >
> > >    reg:
> > >      maxItems: 1
> > > @@ -28,11 +29,16 @@ properties:
> > >        - const: ref
> > >
> > >    resets:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    maxItems: 2
> > >
> > >    reset-names:
> > > -    items:
> > > -      - const: pciephy
> > > +    oneOf:
> > > +      - items:          # for iMX8MM
> > > +          - const: pciephy
> > > +      - items:          # for IMX8MP
> > > +          - const: pciephy
> > > +          - const: perst
> >
> > This does the same thing:
> >
> > minItems: 1
> > items:
> >   - const: pciephy
> >   - const: perst
> >
> Okay, thanks.
> 
Hi Rob:
Do you mean the following definition of reset?
...
  resets:
    minItems: 1

  reset-names:
    minItems: 1
      - const: pciephy
      - const: perst
...
When do the dtbs_check later, it complains like below.
"
CHECK   arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dtb
  DTC     arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb
  CHECK   arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb
/home/richard/work/linux-imx/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dtb: pcie-phy@32f00000: resets: [[83, 24], [83, 25]] is too long
	From schema: /home/richard/work/linux-imx/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
  DTC     arch/arm64/boot/dts/freescale/imx8mp-evk.dtb
  CHECK   arch/arm64/boot/dts/freescale/imx8mp-evk.dtb
/home/richard/work/linux-imx/arch/arm64/boot/dts/freescale/imx8mp-evk.dtb: pcie-phy@32f00000: resets: [[61, 24], [61, 25]] is too long
	From schema: /home/richard/work/linux-imx/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
"

Best Regards
Richard Zhu

> Best Regards
> Richard Zhu
> >
> > >
> > >    fsl,refclk-pad-mode:
> > >      description: |
> > > @@ -60,6 +66,10 @@ properties:
> > >      description: A boolean property indicating the CLKREQ# signal is
> > >        not supported in the board design (optional)
> > >
> > > +  power-domains:
> > > +    description: PCIe PHY  power domain (optional).
> > > +    maxItems: 1
> > > +
> > >  required:
> > >    - "#phy-cells"
> > >    - compatible
> > > --
> > > 2.25.1
> > >
> > >

[PATCH v3 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support

[Richard Zhu]

Add the i.MX8MP PCIe PHY support

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 150 ++++++++++++++-------
 1 file changed, 104 insertions(+), 46 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..3463b4299f2f 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,8 @@
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
 #include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -31,12 +33,10 @@
 #define IMX8MM_PCIE_PHY_CMN_REG065	0x194
 #define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
 #define  ANA_AUX_TX_LVL			GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75	0x1D4
-#define  PCIE_PHY_CMN_REG75_PLL_DONE	0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
+#define  ANA_PLL_DONE			0x3
 #define PCIE_PHY_TRSV_REG5		0x414
-#define  PCIE_PHY_TRSV_REG5_GEN1_DEEMP	0x2D
 #define PCIE_PHY_TRSV_REG6		0x418
-#define  PCIE_PHY_TRSV_REG6_GEN2_DEEMP	0xF
 
 #define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
 #define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +47,29 @@
 #define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
 #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
 
+#define IMX8MP_GPR_REG0			0x0
+#define IMX8MP_GPR_PHY_APB_RST		BIT(4)
+#define IMX8MP_GPR_PHY_INIT_RST		BIT(5)
+
+enum imx8_pcie_phy_type {
+	IMX8MM,
+	IMX8MP,
+};
+
 struct imx8_pcie_phy {
 	void __iomem		*base;
+	struct device		*dev;
 	struct clk		*clk;
 	struct phy		*phy;
+	struct regmap		*hsio_blk_ctrl;
 	struct regmap		*iomuxc_gpr;
 	struct reset_control	*reset;
+	struct reset_control	*perst;
 	u32			refclk_pad_mode;
 	u32			tx_deemph_gen1;
 	u32			tx_deemph_gen2;
 	bool			clkreq_unused;
+	enum imx8_pcie_phy_type	variant;
 };
 
 static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +81,27 @@ static int imx8_pcie_phy_init(struct phy *phy)
 	reset_control_assert(imx8_phy->reset);
 
 	pad_mode = imx8_phy->refclk_pad_mode;
-	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
-			   imx8_phy->clkreq_unused ?
-			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_AUX_EN,
-			   IMX8MM_GPR_PCIE_AUX_EN);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_SSC_EN, 0);
-
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
-			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
-			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
-			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
-	usleep_range(100, 200);
-
-	/* Do the PHY common block reset */
-	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
-			   IMX8MM_GPR_PCIE_CMN_RST,
-			   IMX8MM_GPR_PCIE_CMN_RST);
-	usleep_range(200, 500);
+	switch (imx8_phy->variant) {
+	case IMX8MM:
+		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
+		if (imx8_phy->tx_deemph_gen1)
+			writel(imx8_phy->tx_deemph_gen1,
+			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
+		if (imx8_phy->tx_deemph_gen2)
+			writel(imx8_phy->tx_deemph_gen2,
+			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
+		break;
+	case IMX8MP:
+		reset_control_assert(imx8_phy->perst);
+
+		/* release pcie_phy_apb_reset and pcie_phy_init_resetn */
+		regmap_update_bits(imx8_phy->hsio_blk_ctrl, IMX8MP_GPR_REG0,
+				   IMX8MP_GPR_PHY_APB_RST |
+				   IMX8MP_GPR_PHY_INIT_RST,
+				   IMX8MP_GPR_PHY_APB_RST |
+				   IMX8MP_GPR_PHY_INIT_RST);
+		break;
+	}
 
 	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
 	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +129,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
 	}
 
-	/* Tune PHY de-emphasis setting to pass PCIe compliance. */
-	if (imx8_phy->tx_deemph_gen1)
-		writel(imx8_phy->tx_deemph_gen1,
-		       imx8_phy->base + PCIE_PHY_TRSV_REG5);
-	if (imx8_phy->tx_deemph_gen2)
-		writel(imx8_phy->tx_deemph_gen2,
-		       imx8_phy->base + PCIE_PHY_TRSV_REG6);
+	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+			   imx8_phy->clkreq_unused ?
+			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_AUX_EN,
+			   IMX8MM_GPR_PCIE_AUX_EN);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
+			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
+			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
+	usleep_range(100, 200);
 
-	reset_control_deassert(imx8_phy->reset);
+	/* Do the PHY common block reset */
+	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+			   IMX8MM_GPR_PCIE_CMN_RST,
+			   IMX8MM_GPR_PCIE_CMN_RST);
+
+	switch (imx8_phy->variant) {
+	case IMX8MP:
+		reset_control_deassert(imx8_phy->perst);
+		fallthrough;
+	case IMX8MM:
+		reset_control_deassert(imx8_phy->reset);
+		usleep_range(200, 500);
+		break;
+	}
 
 	/* Polling to check the phy is ready or not. */
-	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
-				 val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
-				 10, 20000);
+	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+				 val, val == ANA_PLL_DONE, 10, 20000);
 	return ret;
 }
 
@@ -160,18 +193,33 @@ static const struct phy_ops imx8_pcie_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+	{.compatible = "fsl,imx8mm-pcie-phy", .data = (void *)IMX8MM},
+	{.compatible = "fsl,imx8mp-pcie-phy", .data = (void *)IMX8MP},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
 static int imx8_pcie_phy_probe(struct platform_device *pdev)
 {
 	struct phy_provider *phy_provider;
 	struct device *dev = &pdev->dev;
+	const struct of_device_id *of_id;
 	struct device_node *np = dev->of_node;
 	struct imx8_pcie_phy *imx8_phy;
 	struct resource *res;
 
+	of_id = of_match_device(imx8_pcie_phy_of_match, dev);
+	if (!of_id)
+		return -EINVAL;
+
 	imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
 	if (!imx8_phy)
 		return -ENOMEM;
 
+	imx8_phy->dev = dev;
+	imx8_phy->variant = (enum imx8_pcie_phy_type)of_id->data;
+
 	/* get PHY refclk pad mode */
 	of_property_read_u32(np, "fsl,refclk-pad-mode",
 			     &imx8_phy->refclk_pad_mode);
@@ -208,6 +256,22 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 		dev_err(dev, "Failed to get PCIEPHY reset control\n");
 		return PTR_ERR(imx8_phy->reset);
 	}
+	if (imx8_phy->variant == IMX8MP) {
+		/* Grab HSIO MIX config register range */
+		imx8_phy->hsio_blk_ctrl =
+			 syscon_regmap_lookup_by_compatible("fsl,imx8mp-hsio-blk-ctrl");
+		if (IS_ERR(imx8_phy->hsio_blk_ctrl)) {
+			dev_err(dev, "Unable to find HSIO MIX registers\n");
+			return PTR_ERR(imx8_phy->hsio_blk_ctrl);
+		}
+
+		imx8_phy->perst =
+			devm_reset_control_get_exclusive(dev, "perst");
+		if (IS_ERR(imx8_phy->perst)) {
+			dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+			return PTR_ERR(imx8_phy->perst);
+		}
+	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	imx8_phy->base = devm_ioremap_resource(dev, res);
@@ -225,12 +289,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
-	{.compatible = "fsl,imx8mm-pcie-phy",},
-	{ },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
 static struct platform_driver imx8_pcie_phy_driver = {
 	.probe	= imx8_pcie_phy_probe,
 	.driver = {
-- 
2.25.1

[PATCH v3 4/6] arm64: dts: imx8mp: add the iMX8MP PCIe support

[Richard Zhu]

Add the i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index fe178b7d063c..a6ba351c4927 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/imx8mp-clock.h>
 #include <dt-bindings/power/imx8mp-power.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -410,7 +411,8 @@ iomuxc: pinctrl@30330000 {
 			};
 
 			gpr: iomuxc-gpr@30340000 {
-				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+				compatible = "fsl,imx8mp-iomuxc-gpr",
+					     "fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x30340000 0x10000>;
 			};
 
@@ -1084,6 +1086,17 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
 				#power-domain-cells = <1>;
 			};
 
+			pcie_phy: pcie-phy@32f00000 {
+				compatible = "fsl,imx8mp-pcie-phy";
+				reg = <0x32f00000 0x10000>;
+				resets = <&src IMX8MP_RESET_PCIEPHY>,
+					 <&src IMX8MP_RESET_PCIEPHY_PERST>;
+				reset-names = "pciephy", "perst";
+				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
 			hsio_blk_ctrl: blk-ctrl@32f10000 {
 				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
 				reg = <0x32f10000 0x24>;
@@ -1099,6 +1112,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
 			};
 		};
 
+		pcie: pcie@33800000 {
+			compatible = "fsl,imx8mp-pcie";
+			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+				   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,max-link-speed = <3>;
+			linux,pci-domain = <0>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "apps", "turnoff";
+			phys = <&pcie_phy>;
+			phy-names = "pcie-phy";
+			status = "disabled";
+		};
+
 		gpu3d: gpu@38000000 {
 			compatible = "vivante,gc";
 			reg = <0x38000000 0x8000>;
-- 
2.25.1

[PATCH v3 5/6] arm64: dts: imx8mp-evk: Add PCIe support

[Richard Zhu]

Add PCIe support on i.MX8MP EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 ++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f6b017ab5f53..defc92a8bb60 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/phy/phy-imx8-pcie.h>
 #include "imx8mp.dtsi"
 
 / {
@@ -33,6 +34,12 @@ memory@40000000 {
 		      <0x1 0x00000000 0 0xc0000000>;
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};
+
 	reg_can1_stby: regulator-can1-stby {
 		compatible = "regulator-fixed";
 		regulator-name = "can1-stby";
@@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
 		enable-active-high;
 	};
 
+	reg_pcie0: regulator-pcie {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -350,6 +368,28 @@ &i2c5 {
 	 */
 };
 
+&pcie_phy {
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pcie{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>,
+		 <&clk IMX8MP_CLK_HSIO_AXI>;
+	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+	assigned-clock-rates = <10000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+	vpcie-supply = <&reg_pcie0>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -502,6 +542,19 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61 /* open drain, pull up */
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
-- 
2.25.1

[PATCH v3 6/6] PCI: imx6: Add the iMX8MP PCIe support

[Richard Zhu]

Add the i.MX8MP PCIe support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6e5debdbc55b..786f5737ca6a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -51,6 +51,7 @@ enum imx6_pcie_variants {
 	IMX7D,
 	IMX8MQ,
 	IMX8MM,
+	IMX8MP,
 };
 
 #define IMX6_PCIE_FLAG_IMX6_PHY			BIT(0)
@@ -150,7 +151,8 @@ struct imx6_pcie {
 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 {
 	WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
-		imx6_pcie->drvdata->variant != IMX8MM);
+		imx6_pcie->drvdata->variant != IMX8MM &&
+		imx6_pcie->drvdata->variant != IMX8MP);
 	return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 }
 
@@ -301,6 +303,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MM:
+	case IMX8MP:
 		/*
 		 * The PHY initialization had been done in the PHY
 		 * driver, break here directly.
@@ -558,6 +561,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX8MM:
 	case IMX8MQ:
+	case IMX8MP:
 		ret = clk_prepare_enable(imx6_pcie->pcie_aux);
 		if (ret) {
 			dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -602,6 +606,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX8MM:
 	case IMX8MQ:
+	case IMX8MP:
 		clk_disable_unprepare(imx6_pcie->pcie_aux);
 		break;
 	default:
@@ -669,6 +674,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 		reset_control_assert(imx6_pcie->pciephy_reset);
 		fallthrough;
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
 	case IMX6SX:
@@ -744,6 +750,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX6Q:		/* Nothing to do */
 	case IMX8MM:
+	case IMX8MP:
 		break;
 	}
 
@@ -793,6 +800,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
 	case IMX7D:
 	case IMX8MQ:
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_deassert(imx6_pcie->apps_reset);
 		break;
 	}
@@ -812,6 +820,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
 	case IMX7D:
 	case IMX8MQ:
 	case IMX8MM:
+	case IMX8MP:
 		reset_control_assert(imx6_pcie->apps_reset);
 		break;
 	}
@@ -1179,6 +1188,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 		}
 		break;
 	case IMX8MM:
+	case IMX8MP:
 		imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
 		if (IS_ERR(imx6_pcie->pcie_aux))
 			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1320,6 +1330,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
 		.variant = IMX8MM,
 		.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
 	},
+	[IMX8MP] = {
+		.variant = IMX8MP,
+		.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
+	},
 };
 
 static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1329,6 +1343,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
 	{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
 	{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
+	{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
 	{},
 };
 
-- 
2.25.1

Re: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Marek Vasut]

On 8/18/22 09:02, Richard Zhu wrote:
> Based on the 6.0-rc1 of the pci/next branch.
> This series adds the i.MX8MP PCIe support and had been tested on i.MX8MP
> EVK board when one PCIe NVME device is used.
> 
> - i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
>    Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
>    And share as much as possible codes with i.MX8MM PCIe PHY.
> - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
>    driver.
> 
> Main changes v2-->v3:
> - Fix the schema checking error in the PHY dt-binding patch.
> - Inspired by Lucas, the PLL configurations might not required when
>    external OSC is used as PCIe referrence clock. It's true. Remove all
>    the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
>    with one NVME device is used.
> - Drop the #4 patch of v2, since it had been applied by Rob.
> 
> Main changes v1-->v2:
> - It's my fault forget including Vinod, re-send v2 after include Vinod
>    and linux-phy@lists.infradead.org.
> - List the basements of this patch-set. The branch, codes changes and so on.
> - Clean up some useless register and bit definitions in #3 patch.
> 
> Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 +++++++--
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53 +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46 ++++++++++++++++++++++++-
> drivers/pci/controller/dwc/pci-imx6.c                        |  17 +++++++++-
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
> drivers/reset/reset-imx7.c                                   |   1 +
> 6 files changed, 232 insertions(+), 51 deletions(-)

For the entire series:

Tested-by: Marek Vasut <marex@denx.de>

Thanks !

RE: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Hongxing Zhu]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: 2022年8月18日 17:20
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
> l.stach@pengutronix.de; bhelgaas@google.com; lorenzo.pieralisi@arm.com;
> robh@kernel.org; shawnguo@kernel.org; vkoul@kernel.org;
> alexander.stein@ew.tq-group.com
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 0/6] Add the iMX8MP PCIe support
> 
> On 8/18/22 09:02, Richard Zhu wrote:
> > Based on the 6.0-rc1 of the pci/next branch.
> > This series adds the i.MX8MP PCIe support and had been tested on
> > i.MX8MP EVK board when one PCIe NVME device is used.
> >
> > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> i.MX8MQ/i.MX8MM.
> >    Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> >    And share as much as possible codes with i.MX8MM PCIe PHY.
> > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> >    driver.
> >
> > Main changes v2-->v3:
> > - Fix the schema checking error in the PHY dt-binding patch.
> > - Inspired by Lucas, the PLL configurations might not required when
> >    external OSC is used as PCIe referrence clock. It's true. Remove all
> >    the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
> board
> >    with one NVME device is used.
> > - Drop the #4 patch of v2, since it had been applied by Rob.
> >
> > Main changes v1-->v2:
> > - It's my fault forget including Vinod, re-send v2 after include Vinod
> >    and linux-phy@lists.infradead.org.
> > - List the basements of this patch-set. The branch, codes changes and so on.
> > - Clean up some useless register and bit definitions in #3 patch.
> >
> > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16
> +++++++--
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53
> +++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46
> ++++++++++++++++++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c                        |  17
> +++++++++-
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> ------------------
> > drivers/reset/reset-imx7.c                                   |   1 +
> > 6 files changed, 232 insertions(+), 51 deletions(-)
> 
> For the entire series:
> 
> Tested-by: Marek Vasut <marex@denx.de>
> 
Hi Marek:
Thanks for your kindly help to test it.

Best Regards
Richard Zhu

> Thanks !

Re: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Marek Vasut]

On 8/18/22 12:53, Hongxing Zhu wrote:
>> -----Original Message-----
>> From: Marek Vasut <marex@denx.de>
>> Sent: 2022年8月18日 17:20
>> To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de;
>> l.stach@pengutronix.de; bhelgaas@google.com; lorenzo.pieralisi@arm.com;
>> robh@kernel.org; shawnguo@kernel.org; vkoul@kernel.org;
>> alexander.stein@ew.tq-group.com
>> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
>> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
>> <linux-imx@nxp.com>
>> Subject: Re: [PATCH v3 0/6] Add the iMX8MP PCIe support
>>
>> On 8/18/22 09:02, Richard Zhu wrote:
>>> Based on the 6.0-rc1 of the pci/next branch.
>>> This series adds the i.MX8MP PCIe support and had been tested on
>>> i.MX8MP EVK board when one PCIe NVME device is used.
>>>
>>> - i.MX8MP PCIe has reversed initial PERST bit value refer to
>> i.MX8MQ/i.MX8MM.
>>>     Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
>>> - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
>>>     And share as much as possible codes with i.MX8MM PCIe PHY.
>>> - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
>>>     driver.
>>>
>>> Main changes v2-->v3:
>>> - Fix the schema checking error in the PHY dt-binding patch.
>>> - Inspired by Lucas, the PLL configurations might not required when
>>>     external OSC is used as PCIe referrence clock. It's true. Remove all
>>>     the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
>> board
>>>     with one NVME device is used.
>>> - Drop the #4 patch of v2, since it had been applied by Rob.
>>>
>>> Main changes v1-->v2:
>>> - It's my fault forget including Vinod, re-send v2 after include Vinod
>>>     and linux-phy@lists.infradead.org.
>>> - List the basements of this patch-set. The branch, codes changes and so on.
>>> - Clean up some useless register and bit definitions in #3 patch.
>>>
>>> Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16
>> +++++++--
>>> arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53
>> +++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46
>> ++++++++++++++++++++++++-
>>> drivers/pci/controller/dwc/pci-imx6.c                        |  17
>> +++++++++-
>>> drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150
>> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
>> ------------------
>>> drivers/reset/reset-imx7.c                                   |   1 +
>>> 6 files changed, 232 insertions(+), 51 deletions(-)
>>
>> For the entire series:
>>
>> Tested-by: Marek Vasut <marex@denx.de>
>>
> Hi Marek:
> Thanks for your kindly help to test it.

Gladly. Thank you for your continued effort .

Re: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Richard Leitner]

Hi Richard,

On Thu, Aug 18, 2022 at 03:02:27PM +0800, Richard Zhu wrote:
> Based on the 6.0-rc1 of the pci/next branch. 
> This series adds the i.MX8MP PCIe support and had been tested on i.MX8MP
> EVK board when one PCIe NVME device is used.
> 
> - i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
>   Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
>   And share as much as possible codes with i.MX8MM PCIe PHY.
> - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
>   driver.
> 
> Main changes v2-->v3:
> - Fix the schema checking error in the PHY dt-binding patch.
> - Inspired by Lucas, the PLL configurations might not required when
>   external OSC is used as PCIe referrence clock. It's true. Remove all
>   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
>   with one NVME device is used.
> - Drop the #4 patch of v2, since it had been applied by Rob.
> 
> Main changes v1-->v2:
> - It's my fault forget including Vinod, re-send v2 after include Vinod
>   and linux-phy@lists.infradead.org.
> - List the basements of this patch-set. The branch, codes changes and so on.
> - Clean up some useless register and bit definitions in #3 patch.
> 
> Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 +++++++--
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53 +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46 ++++++++++++++++++++++++-
> drivers/pci/controller/dwc/pci-imx6.c                        |  17 +++++++++-
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
> drivers/reset/reset-imx7.c                                   |   1 +
> 6 files changed, 232 insertions(+), 51 deletions(-)
> 
>  [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
>  [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
>  [PATCH v3 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
>  [PATCH v3 4/6] arm64: dts: imx8mp: add the iMX8MP PCIe support
>  [PATCH v3 5/6] arm64: dts: imx8mp-evk: Add PCIe support
>  [PATCH v3 6/6] PCI: imx6: Add the iMX8MP PCIe support

Thanks for this series!
I've just tested this on our custom i.MX8MP based board with an M.2 SSD
and it seems to work!

Therefore please feel free to add:

Tested-by: Richard Leitner <richard.leitner@skidata.com>

I don't know if it's interesting to you, but here's the dmesg output:

[    0.060405] PCI: CLS 0 bytes, default 64
[    1.252523] ehci-pci: EHCI PCI platform driver
[    1.268608] ohci-pci: OHCI PCI platform driver
[    1.750913] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges:
[    1.758221] imx6q-pcie 33800000.pcie: Parsing ranges property...
[    1.765479] imx6q-pcie 33800000.pcie:       IO 0x001ff80000..0x001ff8ffff -> 0x0000000000
[    1.773695] imx6q-pcie 33800000.pcie:      MEM 0x0018000000..0x001fefffff -> 0x0018000000
[    1.999331] phy phy-32f00000.pcie-phy.1: phy_power_on was called before phy_init
[    2.007562] imx6q-pcie 33800000.pcie: Using 32 MSI vectors
[    2.007626] imx6q-pcie 33800000.pcie: iATU unroll: enabled
[    2.013124] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align 64K, limit 16G
[    2.120921] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
[    2.226533] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
[    2.235492] imx6q-pcie 33800000.pcie: Link up, Gen3
[    2.240380] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
[    2.246066] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
[    2.252437] pci_bus 0000:00: root bus resource [bus 00-ff]
[    2.257937] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    2.264134] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff]
[    2.271019] pci_bus 0000:00: scanning bus
[    2.271045] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
[    2.277070] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[    2.283349] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
[    2.293834] pci 0000:00:00.0: supports D1
[    2.301828] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[    2.308195] pci 0000:00:00.0: PME# disabled
[    2.308348] pci 0000:00:00.0: vgaarb: pci_notify
[    2.310109] pci_bus 0000:00: fixups for bus
[    2.310117] pci 0000:00:00.0: scanning [bus 01-ff] behind bridge, pass 0
[    2.310178] pci_bus 0000:01: scanning bus
[    2.310244] pci 0000:01:00.0: [126f:2263] type 00 class 0x010802
[    2.316325] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
[    2.323535] pci 0000:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
[    2.338620] pci 0000:01:00.0: vgaarb: pci_notify
[    2.347400] pci_bus 0000:01: fixups for bus
[    2.347411] pci_bus 0000:01: bus scan returning with max=01
[    2.347422] pci 0000:00:00.0: scanning [bus 01-ff] behind bridge, pass 1
[    2.347435] pci_bus 0000:00: bus scan returning with max=ff
[    2.347455] pci 0000:00:00.0: BAR 0: assigned [mem 0x18000000-0x180fffff]
[    2.354259] pci 0000:00:00.0: BAR 14: assigned [mem 0x18100000-0x181fffff]
[    2.361146] pci 0000:00:00.0: BAR 6: assigned [mem 0x18200000-0x1820ffff pref]
[    2.368383] pci 0000:01:00.0: BAR 0: assigned [mem 0x18100000-0x18103fff 64bit]
[    2.375728] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    2.380965] pci 0000:00:00.0:   bridge window [mem 0x18100000-0x181fffff]
[    2.387853] pcieport 0000:00:00.0: vgaarb: pci_notify
[    2.387921] pcieport 0000:00:00.0: assign IRQ: got 206
[    2.387984] imx6q-pcie 33800000.pcie: msi#0 address_hi 0x0 address_lo 0x42587000
[    2.388095] pcieport 0000:00:00.0: PME: Signaling with IRQ 207
[    2.394218] pcieport 0000:00:00.0: AER: enabled with IRQ 207
[    2.399963] pcieport 0000:00:00.0: saving config space at offset 0x0 (reading 0xabcd16c3)
[    2.399972] pcieport 0000:00:00.0: saving config space at offset 0x4 (reading 0x100507)
[    2.399979] pcieport 0000:00:00.0: saving config space at offset 0x8 (reading 0x6040001)
[    2.399985] pcieport 0000:00:00.0: saving config space at offset 0xc (reading 0x10000)
[    2.399992] pcieport 0000:00:00.0: saving config space at offset 0x10 (reading 0x18000000)
[    2.399998] pcieport 0000:00:00.0: saving config space at offset 0x14 (reading 0x0)
[    2.400005] pcieport 0000:00:00.0: saving config space at offset 0x18 (reading 0xff0100)
[    2.400011] pcieport 0000:00:00.0: saving config space at offset 0x1c (reading 0xf0)
[    2.400018] pcieport 0000:00:00.0: saving config space at offset 0x20 (reading 0x18101810)
[    2.400024] pcieport 0000:00:00.0: saving config space at offset 0x24 (reading 0xfff0)
[    2.400031] pcieport 0000:00:00.0: saving config space at offset 0x28 (reading 0x0)
[    2.400037] pcieport 0000:00:00.0: saving config space at offset 0x2c (reading 0x0)
[    2.400043] pcieport 0000:00:00.0: saving config space at offset 0x30 (reading 0x0)
[    2.400049] pcieport 0000:00:00.0: saving config space at offset 0x34 (reading 0x40)
[    2.400056] pcieport 0000:00:00.0: saving config space at offset 0x38 (reading 0x0)
[    2.400062] pcieport 0000:00:00.0: saving config space at offset 0x3c (reading 0x201ce)
[    2.400091] pcieport 0000:00:00.0: vgaarb: pci_notify
[    2.400192] nvme 0000:01:00.0: vgaarb: pci_notify
[    2.400230] nvme 0000:01:00.0: assign IRQ: got 206
[    2.400431] nvme nvme0: pci function 0000:01:00.0
[    2.405166] nvme 0000:01:00.0: vgaarb: pci_notify
[    2.405178] nvme 0000:01:00.0: enabling device (0000 -> 0002)
[    2.410959] nvme 0000:01:00.0: enabling bus mastering
[    2.411068] imx6q-pcie 33800000.pcie: msi#1 address_hi 0x0 address_lo 0x42587000
[    2.411132] nvme 0000:01:00.0: saving config space at offset 0x0 (reading 0x2263126f)
[    2.411142] nvme 0000:01:00.0: saving config space at offset 0x4 (reading 0x100406)
[    2.411151] nvme 0000:01:00.0: saving config space at offset 0x8 (reading 0x1080203)
[    2.411162] nvme 0000:01:00.0: saving config space at offset 0xc (reading 0x0)
[    2.411172] nvme 0000:01:00.0: saving config space at offset 0x10 (reading 0x18100004)
[    2.411184] nvme 0000:01:00.0: saving config space at offset 0x14 (reading 0x0)
[    2.411194] nvme 0000:01:00.0: saving config space at offset 0x18 (reading 0x0)
[    2.411205] nvme 0000:01:00.0: saving config space at offset 0x1c (reading 0x0)
[    2.411216] nvme 0000:01:00.0: saving config space at offset 0x20 (reading 0x0)
[    2.411226] nvme 0000:01:00.0: saving config space at offset 0x24 (reading 0x0)
[    2.411237] nvme 0000:01:00.0: saving config space at offset 0x28 (reading 0x0)
[    2.411247] nvme 0000:01:00.0: saving config space at offset 0x2c (reading 0x22631dee)
[    2.411258] nvme 0000:01:00.0: saving config space at offset 0x30 (reading 0x0)
[    2.411269] nvme 0000:01:00.0: saving config space at offset 0x34 (reading 0x40)
[    2.411280] nvme 0000:01:00.0: saving config space at offset 0x38 (reading 0x0)
[    2.411290] nvme 0000:01:00.0: saving config space at offset 0x3c (reading 0x1ce)
[    2.415562] nvme nvme0: missing or invalid SUBNQN field.
[    2.428381] nvme nvme0: allocated 64 MiB host memory buffer.
[    2.436360] imx6q-pcie 33800000.pcie: msi#1 address_hi 0x0 address_lo 0x42587000
[    2.436415] imx6q-pcie 33800000.pcie: msi#2 address_hi 0x0 address_lo 0x42587000
[    2.436453] imx6q-pcie 33800000.pcie: msi#3 address_hi 0x0 address_lo 0x42587000
[    2.436491] imx6q-pcie 33800000.pcie: msi#4 address_hi 0x0 address_lo 0x42587000
[    2.436529] imx6q-pcie 33800000.pcie: msi#5 address_hi 0x0 address_lo 0x42587000
[    2.442960] nvme nvme0: 4/0/0 default/read/poll queues
[    2.452699] nvme nvme0: Ignoring bogus Namespace Identifiers
[    2.459882]  nvme0n1: p1

regards;rl

RE: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Hongxing Zhu]

> -----Original Message-----
> From: Richard Leitner <richard.leitner@linux.dev>
> Sent: 2022年8月25日 20:23
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> vkoul@kernel.org; alexander.stein@ew.tq-group.com; marex@denx.de;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 0/6] Add the iMX8MP PCIe support
> 
> Hi Richard,
> 
> On Thu, Aug 18, 2022 at 03:02:27PM +0800, Richard Zhu wrote:
> > Based on the 6.0-rc1 of the pci/next branch.
> > This series adds the i.MX8MP PCIe support and had been tested on
> > i.MX8MP EVK board when one PCIe NVME device is used.
> >
> > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> i.MX8MQ/i.MX8MM.
> >   Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> >   And share as much as possible codes with i.MX8MM PCIe PHY.
> > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> >   driver.
> >
> > Main changes v2-->v3:
> > - Fix the schema checking error in the PHY dt-binding patch.
> > - Inspired by Lucas, the PLL configurations might not required when
> >   external OSC is used as PCIe referrence clock. It's true. Remove all
> >   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
> board
> >   with one NVME device is used.
> > - Drop the #4 patch of v2, since it had been applied by Rob.
> >
> > Main changes v1-->v2:
> > - It's my fault forget including Vinod, re-send v2 after include Vinod
> >   and linux-phy@lists.infradead.org.
> > - List the basements of this patch-set. The branch, codes changes and so on.
> > - Clean up some useless register and bit definitions in #3 patch.
> >
> > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16
> +++++++--
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53
> +++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi                    |  46
> ++++++++++++++++++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c                        |  17
> +++++++++-
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   | 150
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> ------------------
> > drivers/reset/reset-imx7.c                                   |   1 +
> > 6 files changed, 232 insertions(+), 51 deletions(-)
> >
> >  [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
> > [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding  [PATCH v3
> > 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY  [PATCH v3 4/6]
> > arm64: dts: imx8mp: add the iMX8MP PCIe support  [PATCH v3 5/6] arm64:
> > dts: imx8mp-evk: Add PCIe support  [PATCH v3 6/6] PCI: imx6: Add the
> > iMX8MP PCIe support
> 
> Thanks for this series!
> I've just tested this on our custom i.MX8MP based board with an M.2 SSD and
> it seems to work!
> 
> Therefore please feel free to add:
> 
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
It's great.
Thanks a lot for your kindly help.

Best Regards
Richard Zhu

> 
> I don't know if it's interesting to you, but here's the dmesg output:
> 
> [    0.060405] PCI: CLS 0 bytes, default 64
> [    1.252523] ehci-pci: EHCI PCI platform driver
> [    1.268608] ohci-pci: OHCI PCI platform driver
> [    1.750913] imx6q-pcie 33800000.pcie: host bridge
> /soc@0/pcie@33800000 ranges:
> [    1.758221] imx6q-pcie 33800000.pcie: Parsing ranges property...
> [    1.765479] imx6q-pcie 33800000.pcie:       IO
> 0x001ff80000..0x001ff8ffff -> 0x0000000000
> [    1.773695] imx6q-pcie 33800000.pcie:      MEM
> 0x0018000000..0x001fefffff -> 0x0018000000
> [    1.999331] phy phy-32f00000.pcie-phy.1: phy_power_on was called
> before phy_init
> [    2.007562] imx6q-pcie 33800000.pcie: Using 32 MSI vectors
> [    2.007626] imx6q-pcie 33800000.pcie: iATU unroll: enabled
> [    2.013124] imx6q-pcie 33800000.pcie: iATU regions: 4 ob, 4 ib, align 64K,
> limit 16G
> [    2.120921] imx6q-pcie 33800000.pcie: PCIe Gen.1 x1 link up
> [    2.226533] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> [    2.235492] imx6q-pcie 33800000.pcie: Link up, Gen3
> [    2.240380] imx6q-pcie 33800000.pcie: PCIe Gen.3 x1 link up
> [    2.246066] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00
> [    2.252437] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.257937] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
> [    2.264134] pci_bus 0000:00: root bus resource [mem
> 0x18000000-0x1fefffff]
> [    2.271019] pci_bus 0000:00: scanning bus
> [    2.271045] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
> [    2.277070] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
> [    2.283349] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff
> pref]
> [    2.293834] pci 0000:00:00.0: supports D1
> [    2.301828] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
> [    2.308195] pci 0000:00:00.0: PME# disabled
> [    2.308348] pci 0000:00:00.0: vgaarb: pci_notify
> [    2.310109] pci_bus 0000:00: fixups for bus
> [    2.310117] pci 0000:00:00.0: scanning [bus 01-ff] behind bridge, pass 0
> [    2.310178] pci_bus 0000:01: scanning bus
> [    2.310244] pci 0000:01:00.0: [126f:2263] type 00 class 0x010802
> [    2.316325] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff
> 64bit]
> [    2.323535] pci 0000:01:00.0: 7.876 Gb/s available PCIe bandwidth,
> limited by 8.0 GT/s PCIe x1 link at 0000:00:00.0 (capable of 31.504 Gb/s with
> 8.0 GT/s PCIe x4 link)
> [    2.338620] pci 0000:01:00.0: vgaarb: pci_notify
> [    2.347400] pci_bus 0000:01: fixups for bus
> [    2.347411] pci_bus 0000:01: bus scan returning with max=01
> [    2.347422] pci 0000:00:00.0: scanning [bus 01-ff] behind bridge, pass 1
> [    2.347435] pci_bus 0000:00: bus scan returning with max=ff
> [    2.347455] pci 0000:00:00.0: BAR 0: assigned [mem
> 0x18000000-0x180fffff]
> [    2.354259] pci 0000:00:00.0: BAR 14: assigned [mem
> 0x18100000-0x181fffff]
> [    2.361146] pci 0000:00:00.0: BAR 6: assigned [mem
> 0x18200000-0x1820ffff pref]
> [    2.368383] pci 0000:01:00.0: BAR 0: assigned [mem
> 0x18100000-0x18103fff 64bit]
> [    2.375728] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.380965] pci 0000:00:00.0:   bridge window [mem
> 0x18100000-0x181fffff]
> [    2.387853] pcieport 0000:00:00.0: vgaarb: pci_notify
> [    2.387921] pcieport 0000:00:00.0: assign IRQ: got 206
> [    2.387984] imx6q-pcie 33800000.pcie: msi#0 address_hi 0x0 address_lo
> 0x42587000
> [    2.388095] pcieport 0000:00:00.0: PME: Signaling with IRQ 207
> [    2.394218] pcieport 0000:00:00.0: AER: enabled with IRQ 207
> [    2.399963] pcieport 0000:00:00.0: saving config space at offset 0x0
> (reading 0xabcd16c3)
> [    2.399972] pcieport 0000:00:00.0: saving config space at offset 0x4
> (reading 0x100507)
> [    2.399979] pcieport 0000:00:00.0: saving config space at offset 0x8
> (reading 0x6040001)
> [    2.399985] pcieport 0000:00:00.0: saving config space at offset 0xc
> (reading 0x10000)
> [    2.399992] pcieport 0000:00:00.0: saving config space at offset 0x10
> (reading 0x18000000)
> [    2.399998] pcieport 0000:00:00.0: saving config space at offset 0x14
> (reading 0x0)
> [    2.400005] pcieport 0000:00:00.0: saving config space at offset 0x18
> (reading 0xff0100)
> [    2.400011] pcieport 0000:00:00.0: saving config space at offset 0x1c
> (reading 0xf0)
> [    2.400018] pcieport 0000:00:00.0: saving config space at offset 0x20
> (reading 0x18101810)
> [    2.400024] pcieport 0000:00:00.0: saving config space at offset 0x24
> (reading 0xfff0)
> [    2.400031] pcieport 0000:00:00.0: saving config space at offset 0x28
> (reading 0x0)
> [    2.400037] pcieport 0000:00:00.0: saving config space at offset 0x2c
> (reading 0x0)
> [    2.400043] pcieport 0000:00:00.0: saving config space at offset 0x30
> (reading 0x0)
> [    2.400049] pcieport 0000:00:00.0: saving config space at offset 0x34
> (reading 0x40)
> [    2.400056] pcieport 0000:00:00.0: saving config space at offset 0x38
> (reading 0x0)
> [    2.400062] pcieport 0000:00:00.0: saving config space at offset 0x3c
> (reading 0x201ce)
> [    2.400091] pcieport 0000:00:00.0: vgaarb: pci_notify
> [    2.400192] nvme 0000:01:00.0: vgaarb: pci_notify
> [    2.400230] nvme 0000:01:00.0: assign IRQ: got 206
> [    2.400431] nvme nvme0: pci function 0000:01:00.0
> [    2.405166] nvme 0000:01:00.0: vgaarb: pci_notify
> [    2.405178] nvme 0000:01:00.0: enabling device (0000 -> 0002)
> [    2.410959] nvme 0000:01:00.0: enabling bus mastering
> [    2.411068] imx6q-pcie 33800000.pcie: msi#1 address_hi 0x0 address_lo
> 0x42587000
> [    2.411132] nvme 0000:01:00.0: saving config space at offset 0x0 (reading
> 0x2263126f)
> [    2.411142] nvme 0000:01:00.0: saving config space at offset 0x4 (reading
> 0x100406)
> [    2.411151] nvme 0000:01:00.0: saving config space at offset 0x8 (reading
> 0x1080203)
> [    2.411162] nvme 0000:01:00.0: saving config space at offset 0xc (reading
> 0x0)
> [    2.411172] nvme 0000:01:00.0: saving config space at offset 0x10
> (reading 0x18100004)
> [    2.411184] nvme 0000:01:00.0: saving config space at offset 0x14
> (reading 0x0)
> [    2.411194] nvme 0000:01:00.0: saving config space at offset 0x18
> (reading 0x0)
> [    2.411205] nvme 0000:01:00.0: saving config space at offset 0x1c
> (reading 0x0)
> [    2.411216] nvme 0000:01:00.0: saving config space at offset 0x20
> (reading 0x0)
> [    2.411226] nvme 0000:01:00.0: saving config space at offset 0x24
> (reading 0x0)
> [    2.411237] nvme 0000:01:00.0: saving config space at offset 0x28
> (reading 0x0)
> [    2.411247] nvme 0000:01:00.0: saving config space at offset 0x2c
> (reading 0x22631dee)
> [    2.411258] nvme 0000:01:00.0: saving config space at offset 0x30
> (reading 0x0)
> [    2.411269] nvme 0000:01:00.0: saving config space at offset 0x34
> (reading 0x40)
> [    2.411280] nvme 0000:01:00.0: saving config space at offset 0x38
> (reading 0x0)
> [    2.411290] nvme 0000:01:00.0: saving config space at offset 0x3c
> (reading 0x1ce)
> [    2.415562] nvme nvme0: missing or invalid SUBNQN field.
> [    2.428381] nvme nvme0: allocated 64 MiB host memory buffer.
> [    2.436360] imx6q-pcie 33800000.pcie: msi#1 address_hi 0x0 address_lo
> 0x42587000
> [    2.436415] imx6q-pcie 33800000.pcie: msi#2 address_hi 0x0 address_lo
> 0x42587000
> [    2.436453] imx6q-pcie 33800000.pcie: msi#3 address_hi 0x0 address_lo
> 0x42587000
> [    2.436491] imx6q-pcie 33800000.pcie: msi#4 address_hi 0x0 address_lo
> 0x42587000
> [    2.436529] imx6q-pcie 33800000.pcie: msi#5 address_hi 0x0 address_lo
> 0x42587000
> [    2.442960] nvme nvme0: 4/0/0 default/read/poll queues
> [    2.452699] nvme nvme0: Ignoring bogus Namespace Identifiers
> [    2.459882]  nvme0n1: p1
> 
> regards;rl

Re: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Alexander Stein]

Am Donnerstag, 18. August 2022, 09:02:27 CEST schrieb Richard Zhu:
> Based on the 6.0-rc1 of the pci/next branch.
> This series adds the i.MX8MP PCIe support and had been tested on i.MX8MP
> EVK board when one PCIe NVME device is used.
> 
> - i.MX8MP PCIe has reversed initial PERST bit value refer to
> i.MX8MQ/i.MX8MM. Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
>   And share as much as possible codes with i.MX8MM PCIe PHY.
> - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
>   driver.
> 
> Main changes v2-->v3:
> - Fix the schema checking error in the PHY dt-binding patch.
> - Inspired by Lucas, the PLL configurations might not required when
>   external OSC is used as PCIe referrence clock. It's true. Remove all
>   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
>   with one NVME device is used.
> - Drop the #4 patch of v2, since it had been applied by Rob.
> 
> Main changes v1-->v2:
> - It's my fault forget including Vinod, re-send v2 after include Vinod
>   and linux-phy@lists.infradead.org.
> - List the basements of this patch-set. The branch, codes changes and so on.
> - Clean up some useless register and bit definitions in #3 patch.
> 
> Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16 +++++++--
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53
> +++++++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi    
>                |  46 ++++++++++++++++++++++++-
> drivers/pci/controller/dwc/pci-imx6.c                        |  17
> +++++++++- drivers/phy/freescale/phy-fsl-imx8m-pcie.c                   |
> 150
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------
> ------- drivers/reset/reset-imx7.c                                   |   1 +
> 6 files changed, 232 insertions(+), 51 deletions(-)
> 
>  [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
>  [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
>  [PATCH v3 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY
>  [PATCH v3 4/6] arm64: dts: imx8mp: add the iMX8MP PCIe support
>  [PATCH v3 5/6] arm64: dts: imx8mp-evk: Add PCIe support
>  [PATCH v3 6/6] PCI: imx6: Add the iMX8MP PCIe support

On TQMa8MPxl + MBa8MPxL:
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

RE: [PATCH v3 0/6] Add the iMX8MP PCIe support

[Hongxing Zhu]

> -----Original Message-----
> From: Alexander Stein <alexander.stein@ew.tq-group.com>
> Sent: 2022年8月26日 14:22
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> vkoul@kernel.org; marex@denx.de; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 0/6] Add the iMX8MP PCIe support
> 
> Am Donnerstag, 18. August 2022, 09:02:27 CEST schrieb Richard Zhu:
> > Based on the 6.0-rc1 of the pci/next branch.
> > This series adds the i.MX8MP PCIe support and had been tested on
> > i.MX8MP EVK board when one PCIe NVME device is used.
> >
> > - i.MX8MP PCIe has reversed initial PERST bit value refer to
> > i.MX8MQ/i.MX8MM. Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
> > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
> >   And share as much as possible codes with i.MX8MM PCIe PHY.
> > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
> >   driver.
> >
> > Main changes v2-->v3:
> > - Fix the schema checking error in the PHY dt-binding patch.
> > - Inspired by Lucas, the PLL configurations might not required when
> >   external OSC is used as PCIe referrence clock. It's true. Remove all
> >   the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK
> board
> >   with one NVME device is used.
> > - Drop the #4 patch of v2, since it had been applied by Rob.
> >
> > Main changes v1-->v2:
> > - It's my fault forget including Vinod, re-send v2 after include Vinod
> >   and linux-phy@lists.infradead.org.
> > - List the basements of this patch-set. The branch, codes changes and so on.
> > - Clean up some useless register and bit definitions in #3 patch.
> >
> > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml |  16
> +++++++--
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts                 |  53
> > +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi
> >                |  46 ++++++++++++++++++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c                        |  17
> > +++++++++- drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> |
> > 150
> >
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> ------
> > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
> > ------- drivers/reset/reset-imx7.c                                   |
> 1 +
> > 6 files changed, 232 insertions(+), 51 deletions(-)
> >
> >  [PATCH v3 1/6] reset: imx7: Add the iMX8MP PCIe PHY PERST support
> > [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding  [PATCH v3
> > 3/6] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY  [PATCH v3 4/6]
> > arm64: dts: imx8mp: add the iMX8MP PCIe support  [PATCH v3 5/6] arm64:
> > dts: imx8mp-evk: Add PCIe support  [PATCH v3 6/6] PCI: imx6: Add the
> > iMX8MP PCIe support
> 
> On TQMa8MPxl + MBa8MPxL:
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Thanks.

Best Regards
Richard Zhu
> 
>