* [PATCH v9 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding
2022-09-26 6:40 [PATCH v9 0/4] Add the iMX8MP PCIe support Richard Zhu
@ 2022-09-26 6:41 ` Richard Zhu
2022-09-26 6:41 ` [PATCH v9 2/4] phy: freescale: imx8m-pcie: Refine register definitions Richard Zhu
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Richard Zhu @ 2022-09-26 6:41 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY binding.
On i.MX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 2/4] phy: freescale: imx8m-pcie: Refine register definitions
2022-09-26 6:40 [PATCH v9 0/4] Add the iMX8MP PCIe support Richard Zhu
2022-09-26 6:41 ` [PATCH v9 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding Richard Zhu
@ 2022-09-26 6:41 ` Richard Zhu
2022-09-26 6:41 ` [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
2022-09-26 6:41 ` [PATCH v9 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
3 siblings, 0 replies; 7+ messages in thread
From: Richard Zhu @ 2022-09-26 6:41 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
No function changes, refine PHY register definitions.
- Keep align with other CMN PHY registers, refine the definitions of
PHY_CMN_REG75.
- Remove two BIT definitions that are not used at all.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..2377ed307b53 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -31,12 +31,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -131,9 +129,8 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_deassert(imx8_phy->reset);
/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-26 6:40 [PATCH v9 0/4] Add the iMX8MP PCIe support Richard Zhu
2022-09-26 6:41 ` [PATCH v9 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding Richard Zhu
2022-09-26 6:41 ` [PATCH v9 2/4] phy: freescale: imx8m-pcie: Refine register definitions Richard Zhu
@ 2022-09-26 6:41 ` Richard Zhu
2022-09-29 6:32 ` Vinod Koul
2022-09-26 6:41 ` [PATCH v9 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
3 siblings, 1 reply; 7+ messages in thread
From: Richard Zhu @ 2022-09-26 6:41 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
driver.
- Use gpr compatible string to avoid the codes duplications when add
another platform PCIe PHY support.
- Re-orange the codes to let it more flexible and easy to expand.
No functions changes basicly.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 108 +++++++++++++--------
1 file changed, 68 insertions(+), 40 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index 2377ed307b53..9752818fe990 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -45,6 +46,15 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+enum imx8_pcie_phy_type {
+ IMX8MM,
+};
+
+struct imx8_pcie_phy_drvdata {
+ enum imx8_pcie_phy_type variant;
+ const char *gpr;
+};
+
struct imx8_pcie_phy {
void __iomem *base;
struct clk *clk;
@@ -55,6 +65,7 @@ struct imx8_pcie_phy {
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
};
static int imx8_pcie_phy_init(struct phy *phy)
@@ -66,31 +77,17 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);
pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ }
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -118,15 +115,37 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}
- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
- reset_control_deassert(imx8_phy->reset);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);
+
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }
/* Polling to check the phy is ready or not. */
ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
@@ -157,6 +176,19 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct imx8_pcie_phy_drvdata drvdata[] = {
+ [IMX8MM] = {
+ .variant = IMX8MM,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ },
+};
+
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -169,6 +201,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
if (!imx8_phy)
return -ENOMEM;
+ imx8_phy->drvdata = of_device_get_match_data(dev);
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -194,7 +228,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
/* Grab GPR config register range */
imx8_phy->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
if (IS_ERR(imx8_phy->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -222,12 +256,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-26 6:41 ` [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
@ 2022-09-29 6:32 ` Vinod Koul
2022-09-29 8:18 ` Hongxing Zhu
0 siblings, 1 reply; 7+ messages in thread
From: Vinod Koul @ 2022-09-29 6:32 UTC (permalink / raw)
To: Richard Zhu
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, linux-imx
On 26-09-22, 14:41, Richard Zhu wrote:
> To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> driver.
> - Use gpr compatible string to avoid the codes duplications when add
> another platform PCIe PHY support.
> - Re-orange the codes to let it more flexible and easy to expand.
> No functions changes basicly.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 108 +++++++++++++--------
> 1 file changed, 68 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index 2377ed307b53..9752818fe990 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,7 @@
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -45,6 +46,15 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> +enum imx8_pcie_phy_type {
> + IMX8MM,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> + enum imx8_pcie_phy_type variant;
> + const char *gpr;
> +};
> +
> struct imx8_pcie_phy {
> void __iomem *base;
> struct clk *clk;
> @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
> u32 tx_deemph_gen1;
> u32 tx_deemph_gen2;
> bool clkreq_unused;
> + const struct imx8_pcie_phy_drvdata *drvdata;
> };
>
> static int imx8_pcie_phy_init(struct phy *phy)
> @@ -66,31 +77,17 @@ static int imx8_pcie_phy_init(struct phy *phy)
> reset_control_assert(imx8_phy->reset);
>
> pad_mode = imx8_phy->refclk_pad_mode;
> - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> - imx8_phy->clkreq_unused ?
> - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN,
> - IMX8MM_GPR_PCIE_AUX_EN);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> - usleep_range(100, 200);
> -
> - /* Do the PHY common block reset */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_CMN_RST,
> - IMX8MM_GPR_PCIE_CMN_RST);
> - usleep_range(200, 500);
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> + if (imx8_phy->tx_deemph_gen1)
> + writel(imx8_phy->tx_deemph_gen1,
> + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> + if (imx8_phy->tx_deemph_gen2)
> + writel(imx8_phy->tx_deemph_gen2,
> + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + break;
> + }
>
> if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
> @@ -118,15 +115,37 @@ static int imx8_pcie_phy_init(struct phy *phy)
> imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> }
>
> - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> - if (imx8_phy->tx_deemph_gen1)
> - writel(imx8_phy->tx_deemph_gen1,
> - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> - if (imx8_phy->tx_deemph_gen2)
> - writel(imx8_phy->tx_deemph_gen2,
> - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> + imx8_phy->clkreq_unused ?
> + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN,
> + IMX8MM_GPR_PCIE_AUX_EN);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_SSC_EN, 0);
>
> - reset_control_deassert(imx8_phy->reset);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> + IMX8MM_GPR_PCIE_REF_CLK_PLL);
> + usleep_range(100, 200);
> +
> + /* Do the PHY common block reset */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_CMN_RST,
> + IMX8MM_GPR_PCIE_CMN_RST);
> +
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + reset_control_deassert(imx8_phy->reset);
> + usleep_range(200, 500);
> + break;
> + }
>
> /* Polling to check the phy is ready or not. */
> ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
> @@ -157,6 +176,19 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> + [IMX8MM] = {
> + .variant = IMX8MM,
> + .gpr = "fsl,imx8mm-iomuxc-gpr",
> + },
> +};
Pls drop the array...
static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
.variant = IMX8MM,
.gpr = "fsl,imx8mm-iomuxc-gpr",
};
> +
> +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
So this becomes:
{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata },
you can define new structs for newer SoCs
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> +
> static int imx8_pcie_phy_probe(struct platform_device *pdev)
> {
> struct phy_provider *phy_provider;
> @@ -169,6 +201,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> if (!imx8_phy)
> return -ENOMEM;
>
> + imx8_phy->drvdata = of_device_get_match_data(dev);
> +
> /* get PHY refclk pad mode */
> of_property_read_u32(np, "fsl,refclk-pad-mode",
> &imx8_phy->refclk_pad_mode);
> @@ -194,7 +228,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>
> /* Grab GPR config register range */
> imx8_phy->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> dev_err(dev, "unable to find iomuxc registers\n");
> return PTR_ERR(imx8_phy->iomuxc_gpr);
> @@ -222,12 +256,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR_OR_ZERO(phy_provider);
> }
>
> -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> - {.compatible = "fsl,imx8mm-pcie-phy",},
> - { },
> -};
> -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> -
> static struct platform_driver imx8_pcie_phy_driver = {
> .probe = imx8_pcie_phy_probe,
> .driver = {
> --
> 2.25.1
--
~Vinod
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-29 6:32 ` Vinod Koul
@ 2022-09-29 8:18 ` Hongxing Zhu
0 siblings, 0 replies; 7+ messages in thread
From: Hongxing Zhu @ 2022-09-29 8:18 UTC (permalink / raw)
To: Vinod Koul
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, dl-linux-imx
> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 2022年9月29日 14:32
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe
> PHY driver
>
> On 26-09-22, 14:41, Richard Zhu wrote:
> > To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> > driver.
> > - Use gpr compatible string to avoid the codes duplications when add
> > another platform PCIe PHY support.
> > - Re-orange the codes to let it more flexible and easy to expand.
> > No functions changes basicly.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 108
> > +++++++++++++--------
> > 1 file changed, 68 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index 2377ed307b53..9752818fe990 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,7 @@
> > #include <linux/mfd/syscon.h>
> > #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > #include <linux/module.h>
> > +#include <linux/of_device.h>
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > @@ -45,6 +46,15 @@
> > #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> > #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > + IMX8MM,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > + enum imx8_pcie_phy_type variant;
> > + const char *gpr;
> > +};
> > +
> > struct imx8_pcie_phy {
> > void __iomem *base;
> > struct clk *clk;
> > @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
> > u32 tx_deemph_gen1;
> > u32 tx_deemph_gen2;
> > bool clkreq_unused;
> > + const struct imx8_pcie_phy_drvdata *drvdata;
> > };
> >
> > static int imx8_pcie_phy_init(struct phy *phy) @@ -66,31 +77,17 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > reset_control_assert(imx8_phy->reset);
> >
> > pad_mode = imx8_phy->refclk_pad_mode;
> > - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > - imx8_phy->clkreq_unused ?
> > - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN,
> > - IMX8MM_GPR_PCIE_AUX_EN);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > - usleep_range(100, 200);
> > -
> > - /* Do the PHY common block reset */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_CMN_RST,
> > - IMX8MM_GPR_PCIE_CMN_RST);
> > - usleep_range(200, 500);
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > + if (imx8_phy->tx_deemph_gen1)
> > + writel(imx8_phy->tx_deemph_gen1,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > + if (imx8_phy->tx_deemph_gen2)
> > + writel(imx8_phy->tx_deemph_gen2,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + break;
> > + }
> >
> > if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -118,15
> +115,37 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> > }
> >
> > - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > - if (imx8_phy->tx_deemph_gen1)
> > - writel(imx8_phy->tx_deemph_gen1,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > - if (imx8_phy->tx_deemph_gen2)
> > - writel(imx8_phy->tx_deemph_gen2,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > + imx8_phy->clkreq_unused ?
> > + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN,
> > + IMX8MM_GPR_PCIE_AUX_EN);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_SSC_EN, 0);
> >
> > - reset_control_deassert(imx8_phy->reset);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > + IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > + usleep_range(100, 200);
> > +
> > + /* Do the PHY common block reset */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_CMN_RST,
> > + IMX8MM_GPR_PCIE_CMN_RST);
> > +
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + reset_control_deassert(imx8_phy->reset);
> > + usleep_range(200, 500);
> > + break;
> > + }
> >
> > /* Polling to check the phy is ready or not. */
> > ret = readl_poll_timeout(imx8_phy->base +
> > IMX8MM_PCIE_PHY_CMN_REG075, @@ -157,6 +176,19 @@ static const
> struct phy_ops imx8_pcie_phy_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> > + [IMX8MM] = {
> > + .variant = IMX8MM,
> > + .gpr = "fsl,imx8mm-iomuxc-gpr",
> > + },
> > +};
>
> Pls drop the array...
>
> static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
> .variant = IMX8MM,
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> };
>
Okay, thanks.
>
>
> > +
> > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
>
> So this becomes:
>
> {.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata },
>
> you can define new structs for newer SoCs
Okay, would follow this way. Thanks.
Best Regards
Richard Zhu
>
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > +
> > static int imx8_pcie_phy_probe(struct platform_device *pdev) {
> > struct phy_provider *phy_provider;
> > @@ -169,6 +201,8 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > if (!imx8_phy)
> > return -ENOMEM;
> >
> > + imx8_phy->drvdata = of_device_get_match_data(dev);
> > +
> > /* get PHY refclk pad mode */
> > of_property_read_u32(np, "fsl,refclk-pad-mode",
> > &imx8_phy->refclk_pad_mode);
> > @@ -194,7 +228,7 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> >
> > /* Grab GPR config register range */
> > imx8_phy->iomuxc_gpr =
> > - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> > + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> > if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > dev_err(dev, "unable to find iomuxc registers\n");
> > return PTR_ERR(imx8_phy->iomuxc_gpr); @@ -222,12 +256,6 @@
> static
> > int imx8_pcie_phy_probe(struct platform_device *pdev)
> > return PTR_ERR_OR_ZERO(phy_provider); }
> >
> > -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > - {.compatible = "fsl,imx8mm-pcie-phy",},
> > - { },
> > -};
> > -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > -
> > static struct platform_driver imx8_pcie_phy_driver = {
> > .probe = imx8_pcie_phy_probe,
> > .driver = {
> > --
> > 2.25.1
>
> --
> ~Vinod
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v9 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-26 6:40 [PATCH v9 0/4] Add the iMX8MP PCIe support Richard Zhu
` (2 preceding siblings ...)
2022-09-26 6:41 ` [PATCH v9 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
@ 2022-09-26 6:41 ` Richard Zhu
3 siblings, 0 replies; 7+ messages in thread
From: Richard Zhu @ 2022-09-26 6:41 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index 9752818fe990..63636994d673 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -48,6 +48,7 @@
enum imx8_pcie_phy_type {
IMX8MM,
+ IMX8MP,
};
struct imx8_pcie_phy_drvdata {
@@ -60,6 +61,7 @@ struct imx8_pcie_phy {
struct clk *clk;
struct phy *phy;
struct regmap *iomuxc_gpr;
+ struct reset_control *perst;
struct reset_control *reset;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
@@ -87,6 +89,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
writel(imx8_phy->tx_deemph_gen2,
imx8_phy->base + PCIE_PHY_TRSV_REG6);
break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+ break;
}
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
@@ -141,6 +146,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
IMX8MM_GPR_PCIE_CMN_RST);
switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
case IMX8MM:
reset_control_deassert(imx8_phy->reset);
usleep_range(200, 500);
@@ -181,10 +189,16 @@ static const struct imx8_pcie_phy_drvdata drvdata[] = {
.variant = IMX8MM,
.gpr = "fsl,imx8mm-iomuxc-gpr",
},
+
+ [IMX8MP] = {
+ .variant = IMX8MP,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
};
static const struct of_device_id imx8_pcie_phy_of_match[] = {
{.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
{ },
};
MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
@@ -240,6 +254,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
if (IS_ERR(imx8_phy->base))
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread