* [PATCH v10 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding
2022-09-29 8:36 [PATCH v10 0/4] Add the iMX8MP PCIe support Richard Zhu
@ 2022-09-29 8:36 ` Richard Zhu
2022-09-29 8:37 ` [PATCH v10 2/4] phy: freescale: imx8m-pcie: Refine register definitions Richard Zhu
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2022-09-29 8:36 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY binding.
On i.MX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v10 2/4] phy: freescale: imx8m-pcie: Refine register definitions
2022-09-29 8:36 [PATCH v10 0/4] Add the iMX8MP PCIe support Richard Zhu
2022-09-29 8:36 ` [PATCH v10 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding Richard Zhu
@ 2022-09-29 8:37 ` Richard Zhu
2022-09-29 8:37 ` [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
2022-09-29 8:37 ` [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
3 siblings, 0 replies; 9+ messages in thread
From: Richard Zhu @ 2022-09-29 8:37 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
No function changes, refine PHY register definitions.
- Keep align with other CMN PHY registers, refine the definitions of
PHY_CMN_REG75.
- Remove two BIT definitions that are not used at all.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..2377ed307b53 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -31,12 +31,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -131,9 +129,8 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_deassert(imx8_phy->reset);
/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-29 8:36 [PATCH v10 0/4] Add the iMX8MP PCIe support Richard Zhu
2022-09-29 8:36 ` [PATCH v10 1/4] dt-binding: phy: Add i.MX8MP PCIe PHY binding Richard Zhu
2022-09-29 8:37 ` [PATCH v10 2/4] phy: freescale: imx8m-pcie: Refine register definitions Richard Zhu
@ 2022-09-29 8:37 ` Richard Zhu
2022-09-30 8:28 ` Ahmad Fatoum
2022-09-29 8:37 ` [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
3 siblings, 1 reply; 9+ messages in thread
From: Richard Zhu @ 2022-09-29 8:37 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
driver.
- Use gpr compatible string to avoid the codes duplications when add
another platform PCIe PHY support.
- Re-orange the codes to let it more flexible and easy to expand.
No functions changes basicly.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106 +++++++++++++--------
1 file changed, 66 insertions(+), 40 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index 2377ed307b53..59b46a4ae069 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,7 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -45,6 +46,15 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+enum imx8_pcie_phy_type {
+ IMX8MM,
+};
+
+struct imx8_pcie_phy_drvdata {
+ enum imx8_pcie_phy_type variant;
+ const char *gpr;
+};
+
struct imx8_pcie_phy {
void __iomem *base;
struct clk *clk;
@@ -55,6 +65,7 @@ struct imx8_pcie_phy {
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
};
static int imx8_pcie_phy_init(struct phy *phy)
@@ -66,31 +77,17 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);
pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ }
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -118,15 +115,37 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}
- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
- reset_control_deassert(imx8_phy->reset);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);
+
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }
/* Polling to check the phy is ready or not. */
ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
@@ -157,6 +176,17 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
+ .variant = IMX8MM,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -169,6 +199,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
if (!imx8_phy)
return -ENOMEM;
+ imx8_phy->drvdata = of_device_get_match_data(dev);
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -194,7 +226,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
/* Grab GPR config register range */
imx8_phy->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
if (IS_ERR(imx8_phy->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -222,12 +254,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-29 8:37 ` [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
@ 2022-09-30 8:28 ` Ahmad Fatoum
2022-10-03 5:14 ` Hongxing Zhu
0 siblings, 1 reply; 9+ messages in thread
From: Ahmad Fatoum @ 2022-09-30 8:28 UTC (permalink / raw)
To: Richard Zhu, vkoul, p.zabel, l.stach, bhelgaas,
lorenzo.pieralisi, robh, shawnguo, alexander.stein, marex,
richard.leitner
Cc: devicetree, linux-pci, linux-kernel, linux-imx, kernel,
linux-phy, linux-arm-kernel
On 29.09.22 09:37, Richard Zhu wrote:
> To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> driver.
> - Use gpr compatible string to avoid the codes duplications when add
> another platform PCIe PHY support.
> - Re-orange the codes to let it more flexible and easy to expand.
Re-arrange
> No functions changes basicly.
No functional change.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106 +++++++++++++--------
> 1 file changed, 66 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index 2377ed307b53..59b46a4ae069 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,7 @@
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> +#include <linux/of_device.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -45,6 +46,15 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> +enum imx8_pcie_phy_type {
> + IMX8MM,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> + enum imx8_pcie_phy_type variant;
Better do indentation on the member name.
> + const char *gpr;
> +};
> +
> struct imx8_pcie_phy {
> void __iomem *base;
> struct clk *clk;
> @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
> u32 tx_deemph_gen1;
> u32 tx_deemph_gen2;
> bool clkreq_unused;
> + const struct imx8_pcie_phy_drvdata *drvdata;
> };
>
> static int imx8_pcie_phy_init(struct phy *phy)
> @@ -66,31 +77,17 @@ static int imx8_pcie_phy_init(struct phy *phy)
> reset_control_assert(imx8_phy->reset);
>
> pad_mode = imx8_phy->refclk_pad_mode;
> - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> - imx8_phy->clkreq_unused ?
> - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN,
> - IMX8MM_GPR_PCIE_AUX_EN);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> - usleep_range(100, 200);
> -
> - /* Do the PHY common block reset */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_CMN_RST,
> - IMX8MM_GPR_PCIE_CMN_RST);
> - usleep_range(200, 500);
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> + if (imx8_phy->tx_deemph_gen1)
> + writel(imx8_phy->tx_deemph_gen1,
> + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> + if (imx8_phy->tx_deemph_gen2)
> + writel(imx8_phy->tx_deemph_gen2,
> + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + break;
> + }
If you say no functional change intended, I'd expect that register
writes happen in the same sequence. It might be ok, that you do
this tuning here, but I think it warrants a mention in the commit
message why it's ok.
Looks good otherwise. With nitpicks addressed:
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver
2022-09-30 8:28 ` Ahmad Fatoum
@ 2022-10-03 5:14 ` Hongxing Zhu
0 siblings, 0 replies; 9+ messages in thread
From: Hongxing Zhu @ 2022-10-03 5:14 UTC (permalink / raw)
To: Ahmad Fatoum, vkoul, p.zabel, l.stach, bhelgaas,
lorenzo.pieralisi, robh, shawnguo, alexander.stein, marex,
richard.leitner
Cc: devicetree, linux-pci, linux-kernel, dl-linux-imx, kernel,
linux-phy, linux-arm-kernel
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Sent: 2022年9月30日 16:29
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; vkoul@kernel.org;
> p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev
> Cc: devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; linux-phy@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM
> PCIe PHY driver
>
> On 29.09.22 09:37, Richard Zhu wrote:
> > To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
> > driver.
> > - Use gpr compatible string to avoid the codes duplications when add
> > another platform PCIe PHY support.
> > - Re-orange the codes to let it more flexible and easy to expand.
>
> Re-arrange
Sorry for the spell mistake. Thanks for your review comments.
>
> > No functions changes basicly.
>
> No functional change.
Got that, thanks.
>
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 106
> > +++++++++++++--------
> > 1 file changed, 66 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index 2377ed307b53..59b46a4ae069 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,7 @@
> > #include <linux/mfd/syscon.h>
> > #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > #include <linux/module.h>
> > +#include <linux/of_device.h>
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > @@ -45,6 +46,15 @@
> > #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> > #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > + IMX8MM,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > + enum imx8_pcie_phy_type variant;
>
> Better do indentation on the member name.
Got that, would make them indent later thanks.
>
> > + const char *gpr;
> > +};
> > +
> > struct imx8_pcie_phy {
> > void __iomem *base;
> > struct clk *clk;
> > @@ -55,6 +65,7 @@ struct imx8_pcie_phy {
> > u32 tx_deemph_gen1;
> > u32 tx_deemph_gen2;
> > bool clkreq_unused;
> > + const struct imx8_pcie_phy_drvdata *drvdata;
> > };
> >
> > static int imx8_pcie_phy_init(struct phy *phy) @@ -66,31 +77,17 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > reset_control_assert(imx8_phy->reset);
> >
> > pad_mode = imx8_phy->refclk_pad_mode;
> > - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > - imx8_phy->clkreq_unused ?
> > - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN,
> > - IMX8MM_GPR_PCIE_AUX_EN);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > - usleep_range(100, 200);
> > -
> > - /* Do the PHY common block reset */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_CMN_RST,
> > - IMX8MM_GPR_PCIE_CMN_RST);
> > - usleep_range(200, 500);
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > + if (imx8_phy->tx_deemph_gen1)
> > + writel(imx8_phy->tx_deemph_gen1,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > + if (imx8_phy->tx_deemph_gen2)
> > + writel(imx8_phy->tx_deemph_gen2,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + break;
> > + }
>
> If you say no functional change intended, I'd expect that register writes happen
> in the same sequence. It might be ok, that you do this tuning here, but I think
> it warrants a mention in the commit message why it's ok.
>
>
> Looks good otherwise. With nitpicks addressed:
>
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
Got that, thanks a lot.
Best Regards
Richard Zhu
>
> --
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> |
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> +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-29 8:36 [PATCH v10 0/4] Add the iMX8MP PCIe support Richard Zhu
` (2 preceding siblings ...)
2022-09-29 8:37 ` [PATCH v10 3/4] phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver Richard Zhu
@ 2022-09-29 8:37 ` Richard Zhu
2022-09-30 8:46 ` Ahmad Fatoum
3 siblings, 1 reply; 9+ messages in thread
From: Richard Zhu @ 2022-09-29 8:37 UTC (permalink / raw)
To: vkoul, p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh,
shawnguo, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index 59b46a4ae069..be5e48864c5a 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -48,6 +48,7 @@
enum imx8_pcie_phy_type {
IMX8MM,
+ IMX8MP,
};
struct imx8_pcie_phy_drvdata {
@@ -60,6 +61,7 @@ struct imx8_pcie_phy {
struct clk *clk;
struct phy *phy;
struct regmap *iomuxc_gpr;
+ struct reset_control *perst;
struct reset_control *reset;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
@@ -87,6 +89,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
writel(imx8_phy->tx_deemph_gen2,
imx8_phy->base + PCIE_PHY_TRSV_REG6);
break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+ break;
}
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
@@ -141,6 +146,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
IMX8MM_GPR_PCIE_CMN_RST);
switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
case IMX8MM:
reset_control_deassert(imx8_phy->reset);
usleep_range(200, 500);
@@ -181,8 +189,14 @@ static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
.gpr = "fsl,imx8mm-iomuxc-gpr",
};
+static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
+ .variant = IMX8MP,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+};
+
static const struct of_device_id imx8_pcie_phy_of_match[] = {
{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
{ },
};
MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
@@ -238,6 +252,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
if (IS_ERR(imx8_phy->base))
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-29 8:37 ` [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
@ 2022-09-30 8:46 ` Ahmad Fatoum
2022-10-03 5:15 ` Hongxing Zhu
0 siblings, 1 reply; 9+ messages in thread
From: Ahmad Fatoum @ 2022-09-30 8:46 UTC (permalink / raw)
To: Richard Zhu, vkoul, p.zabel, l.stach, bhelgaas,
lorenzo.pieralisi, robh, shawnguo, alexander.stein, marex,
richard.leitner
Cc: devicetree, linux-pci, linux-kernel, linux-imx, kernel,
linux-phy, linux-arm-kernel
Hi,
On 29.09.22 09:37, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index 59b46a4ae069..be5e48864c5a 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -48,6 +48,7 @@
>
> enum imx8_pcie_phy_type {
> IMX8MM,
> + IMX8MP,
> };
>
> struct imx8_pcie_phy_drvdata {
> @@ -60,6 +61,7 @@ struct imx8_pcie_phy {
> struct clk *clk;
> struct phy *phy;
> struct regmap *iomuxc_gpr;
> + struct reset_control *perst;
> struct reset_control *reset;
> u32 refclk_pad_mode;
> u32 tx_deemph_gen1;
> @@ -87,6 +89,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
> writel(imx8_phy->tx_deemph_gen2,
> imx8_phy->base + PCIE_PHY_TRSV_REG6);
> break;
> + case IMX8MP:
> + reset_control_assert(imx8_phy->perst);
> + break;
> }
>
> if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> @@ -141,6 +146,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
> IMX8MM_GPR_PCIE_CMN_RST);
>
> switch (imx8_phy->drvdata->variant) {
> + case IMX8MP:
> + reset_control_deassert(imx8_phy->perst);
> + fallthrough;
> case IMX8MM:
> reset_control_deassert(imx8_phy->reset);
> usleep_range(200, 500);
> @@ -181,8 +189,14 @@ static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
> .gpr = "fsl,imx8mm-iomuxc-gpr",
> };
>
> +static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
> + .variant = IMX8MP,
> + .gpr = "fsl,imx8mp-iomuxc-gpr",
> +};
> +
> static const struct of_device_id imx8_pcie_phy_of_match[] = {
> {.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
> + {.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
> { },
> };
> MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> @@ -238,6 +252,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR(imx8_phy->reset);
> }
>
> + if (imx8_phy->drvdata->variant == IMX8MP) {
> + imx8_phy->perst =
> + devm_reset_control_get_exclusive(dev, "perst");
> + if (IS_ERR(imx8_phy->perst)) {
> + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> + return PTR_ERR(imx8_phy->perst);
Nitpick: dev_err_probe here would be useful if user forgets to
enable PHY driver. Anyways:
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cheers,
Ahmad
> + }
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx8_phy->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(imx8_phy->base))
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-30 8:46 ` Ahmad Fatoum
@ 2022-10-03 5:15 ` Hongxing Zhu
0 siblings, 0 replies; 9+ messages in thread
From: Hongxing Zhu @ 2022-10-03 5:15 UTC (permalink / raw)
To: Ahmad Fatoum, vkoul, p.zabel, l.stach, bhelgaas,
lorenzo.pieralisi, robh, shawnguo, alexander.stein, marex,
richard.leitner
Cc: devicetree, linux-pci, linux-kernel, dl-linux-imx, kernel,
linux-phy, linux-arm-kernel
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Sent: 2022年9月30日 16:46
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; vkoul@kernel.org;
> p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev
> Cc: devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; linux-phy@lists.infradead.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH v10 4/4] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe
> PHY support
>
> Hi,
>
> On 29.09.22 09:37, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 23
> > ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index 59b46a4ae069..be5e48864c5a 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -48,6 +48,7 @@
> >
> > enum imx8_pcie_phy_type {
> > IMX8MM,
> > + IMX8MP,
> > };
> >
> > struct imx8_pcie_phy_drvdata {
> > @@ -60,6 +61,7 @@ struct imx8_pcie_phy {
> > struct clk *clk;
> > struct phy *phy;
> > struct regmap *iomuxc_gpr;
> > + struct reset_control *perst;
> > struct reset_control *reset;
> > u32 refclk_pad_mode;
> > u32 tx_deemph_gen1;
> > @@ -87,6 +89,9 @@ static int imx8_pcie_phy_init(struct phy *phy)
> > writel(imx8_phy->tx_deemph_gen2,
> > imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > break;
> > + case IMX8MP:
> > + reset_control_assert(imx8_phy->perst);
> > + break;
> > }
> >
> > if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT || @@ -141,6 +146,9
> @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > IMX8MM_GPR_PCIE_CMN_RST);
> >
> > switch (imx8_phy->drvdata->variant) {
> > + case IMX8MP:
> > + reset_control_deassert(imx8_phy->perst);
> > + fallthrough;
> > case IMX8MM:
> > reset_control_deassert(imx8_phy->reset);
> > usleep_range(200, 500);
> > @@ -181,8 +189,14 @@ static const struct imx8_pcie_phy_drvdata
> imx8mm_drvdata = {
> > .gpr = "fsl,imx8mm-iomuxc-gpr",
> > };
> >
> > +static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
> > + .variant = IMX8MP,
> > + .gpr = "fsl,imx8mp-iomuxc-gpr",
> > +};
> > +
> > static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > {.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
> > + {.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); @@ -238,6
> +252,15 @@
> > static int imx8_pcie_phy_probe(struct platform_device *pdev)
> > return PTR_ERR(imx8_phy->reset);
> > }
> >
> > + if (imx8_phy->drvdata->variant == IMX8MP) {
> > + imx8_phy->perst =
> > + devm_reset_control_get_exclusive(dev, "perst");
> > + if (IS_ERR(imx8_phy->perst)) {
> > + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> > + return PTR_ERR(imx8_phy->perst);
>
> Nitpick: dev_err_probe here would be useful if user forgets to enable PHY
> driver. Anyways:
>
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
Okay, got that. Thanks.
Best Regards
Richard Zhu
> Cheers,
> Ahmad
>
> > + }
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > imx8_phy->base = devm_ioremap_resource(dev, res);
> > if (IS_ERR(imx8_phy->base))
>
>
> --
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