From: Li Chen <me@linux.beauty>
To: "Vignesh Raghavendra" <vigneshr@ti.com>,
"Tom Joseph" <tjoseph@cadence.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"\"Krzysztof Wilczyński\"" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-omap <linux-omap@vger.kernel.org>,
linux-pci <linux-pci@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: [PATCH 1/2] PCI: j721e: Allow async probe
Date: Fri, 07 Jul 2023 10:23:14 +0800 [thread overview]
Message-ID: <1892e291fa4.1219137911620526.2248312811348305435@linux.beauty> (raw)
In-Reply-To:
From: Li Chen <lchen@ambarella.com>
I observed that on Ambarella SoC, which also utilizes
the Cadence controller, the boot time increases by 1
second when no endpoints (including switch) are connected
to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
Enabling async probe can eliminate this boot time increase.
I guess j721e also has this issue.
Signed-off-by: Li Chen <lchen@ambarella.com>
---
drivers/pci/controller/cadence/pci-j721e.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index e70213c9060a..660c13bdb606 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -561,6 +561,7 @@ static struct platform_driver j721e_pcie_driver = {
.name = "j721e-pcie",
.of_match_table = of_j721e_pcie_match,
.suppress_bind_attrs = true,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
};
builtin_platform_driver(j721e_pcie_driver);
--
2.34.1
next reply other threads:[~2023-07-07 2:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-07 2:23 Li Chen [this message]
2023-07-11 6:16 ` [PATCH 1/2] PCI: j721e: Allow async probe Verma, Achal
2023-07-11 8:43 ` Li Chen
2023-07-12 8:27 ` [EXTERNAL] " Verma, Achal
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