[pci:pci/virtualization 10/11] drivers//pci/quirks.c:3705:13: error: implicit declaration of function 'readq'; did you mean 'readl'?

[pci:pci/virtualization 10/11] drivers//pci/quirks.c:3705:13: error: implicit declaration of function 'readq'; did you mean 'readl'?

[kbuild test robot]

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/virtualization
head:   00b834ec962e4252846ccfd6f5dabf7c5c8f7297
commit: c66dd92b90ec97e2068cd8e3aa31f4f43a6e6c2b [10/11] PCI: Disable Samsung SM961/PM961 NVMe before FLR
config: i386-randconfig-x002-201831 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
        git checkout c66dd92b90ec97e2068cd8e3aa31f4f43a6e6c2b
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers//pci/quirks.c: In function 'nvme_disable_and_flr':
>> drivers//pci/quirks.c:3705:13: error: implicit declaration of function 'readq'; did you mean 'readl'? [-Werror=implicit-function-declaration]
      u64 cap = readq(bar + NVME_REG_CAP);
                ^~~~~
                readl
   cc1: some warnings being treated as errors

vim +3705 drivers//pci/quirks.c

  3667	
  3668	/*
  3669	 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
  3670	 * FLR where config space reads from the device return -1.  We seem to be
  3671	 * able to avoid this condition if we disable the NVMe controller prior to
  3672	 * FLR.  This quirk is generic for any NVMe class device requiring similar
  3673	 * assistance to quiesce the device prior to FLR.
  3674	 *
  3675	 * NVMe specification: https://nvmexpress.org/resources/specifications/
  3676	 * Revision 1.0e:
  3677	 *    Chapter 2: Required and optional PCI config registers
  3678	 *    Chapter 3: NVMe control registers
  3679	 *    Chapter 7.3: Reset behavior
  3680	 */
  3681	static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
  3682	{
  3683		void __iomem *bar;
  3684		u16 cmd;
  3685		u32 cfg;
  3686	
  3687		if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
  3688		    !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
  3689			return -ENOTTY;
  3690	
  3691		if (probe)
  3692			return 0;
  3693	
  3694		bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
  3695		if (!bar)
  3696			return -ENOTTY;
  3697	
  3698		pci_read_config_word(dev, PCI_COMMAND, &cmd);
  3699		pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
  3700	
  3701		cfg = readl(bar + NVME_REG_CC);
  3702	
  3703		/* Disable controller if enabled */
  3704		if (cfg & NVME_CC_ENABLE) {
> 3705			u64 cap = readq(bar + NVME_REG_CAP);
  3706			unsigned long timeout;
  3707	
  3708			/*
  3709			 * Per nvme_disable_ctrl() skip shutdown notification as it
  3710			 * could complete commands to the admin queue.  We only intend
  3711			 * to quiesce the device before reset.
  3712			 */
  3713			cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
  3714	
  3715			writel(cfg, bar + NVME_REG_CC);
  3716	
  3717			/*
  3718			 * Some controllers require an additional delay here, see
  3719			 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
  3720			 * supported by this quirk.
  3721			 */
  3722	
  3723			/* Cap register provides max timeout in 500ms increments */
  3724			timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
  3725	
  3726			for (;;) {
  3727				u32 status = readl(bar + NVME_REG_CSTS);
  3728	
  3729				/* Ready status becomes zero on disable complete */
  3730				if (!(status & NVME_CSTS_RDY))
  3731					break;
  3732	
  3733				msleep(100);
  3734	
  3735				if (time_after(jiffies, timeout)) {
  3736					pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
  3737					break;
  3738				}
  3739			}
  3740		}
  3741	
  3742		pci_iounmap(dev, bar);
  3743	
  3744		pcie_flr(dev);
  3745	
  3746		return 0;
  3747	}
  3748	

---
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