From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kedar A Dongre <kedar.a.dongre@intel.com>,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports
Date: Wed, 5 Dec 2018 12:40:29 +0200 [thread overview]
Message-ID: <20181205104029.GL2469@lahna.fi.intel.com> (raw)
In-Reply-To: <20181205094818.jmdy2mg6b6is7jy3@wunner.de>
On Wed, Dec 05, 2018 at 10:48:18AM +0100, Lukas Wunner wrote:
> Does the root port have a _RMV and/or _SUN object? We could e.g.
> disallow runtime PM for any bridge with _RMV present and the HPC
> bit not set in the Slot Capabilities.
Unfortunately it does not have either of those methods :/ It pretty much
looks like a "normal root port" from OS perspective.
Below is the ASL related to the root port (RP05) in question:
Device (RP05)
{
Name (_ADR, 0x001C0004) // _ADR: Address
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (AG5C) /* \_SB_.AG5C */
}
Return (PG5C) /* \_SB_.PG5C */
}
}
Scope (RP05)
{
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
LTRZ = LTR5 /* \LTR5 */
LMSL = PML5 /* \PML5 */
LNSL = PNL5 /* \PNL5 */
OBFZ = OBF5 /* \OBF5 */
}
OperationRegion (PXCS, PCI_Config, 0x00, 0x0480)
Field (PXCS, AnyAcc, NoLock, Preserve)
{
VDID, 32,
Offset (0x50),
L0SE, 1,
, 3,
LDIS, 1,
Offset (0x51),
Offset (0x52),
, 13,
LASX, 1,
Offset (0x5A),
ABPX, 1,
, 2,
PDCX, 1,
, 2,
PDSX, 1,
Offset (0x5B),
Offset (0x60),
Offset (0x62),
PSPX, 1,
PMEP, 1,
Offset (0xA4),
D3HT, 2,
Offset (0xD8),
, 30,
HPEX, 1,
PMEX, 1,
Offset (0xE2),
, 2,
L23E, 1,
L23R, 1,
Offset (0x324),
, 3,
LEDM, 1,
Offset (0x420),
, 30,
DPGE, 1
}
Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
{
Offset (0xDC),
, 30,
HPSX, 1,
PMSX, 1
}
Name (LTRV, Package (0x04)
{
0x00,
0x00,
0x00,
0x00
})
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (0x00)
{
Name (OPTS, Buffer (0x02)
{
0x00, 0x00 // ..
})
CreateBitField (OPTS, 0x00, FUN0)
CreateBitField (OPTS, 0x04, FUN4)
CreateBitField (OPTS, 0x06, FUN6)
CreateBitField (OPTS, 0x08, FUN8)
CreateBitField (OPTS, 0x09, FUN9)
If ((Arg1 >= 0x02))
{
FUN0 = 0x01
If (LTRE)
{
FUN6 = 0x01
}
If (OBFF)
{
FUN4 = 0x01
}
If ((ECR1 == 0x01))
{
If ((Arg1 >= 0x03))
{
FUN8 = 0x01
FUN9 = 0x01
}
}
}
Return (OPTS) /* \_SB_.PC00.RP05._DSM.OPTS */
}
Case (0x04)
{
If ((Arg1 >= 0x02))
{
If (OBFZ)
{
Return (Buffer (0x10)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00 // ........
})
}
Else
{
Return (Buffer (0x10)
{
/* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
/* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // ........
})
}
}
}
Case (0x06)
{
If ((Arg1 >= 0x02))
{
If (LTRZ)
{
If (((LMSL == 0x00) || (LNSL == 0x00)))
{
If ((PCHS == SPTH))
{
LMSL = 0x0846
LNSL = 0x0846
}
ElseIf ((PCHS == SPTL))
{
LMSL = 0x1003
LNSL = 0x1003
}
}
LTRV [0x00] = ((LMSL >> 0x0A) & 0x07)
LTRV [0x01] = (LMSL & 0x03FF)
LTRV [0x02] = ((LNSL >> 0x0A) & 0x07)
LTRV [0x03] = (LNSL & 0x03FF)
Return (LTRV) /* \_SB_.PC00.RP05.LTRV */
}
Else
{
Return (0x00)
}
}
}
Case (0x08)
{
If ((ECR1 == 0x01))
{
If ((Arg1 >= 0x03))
{
Return (0x01)
}
}
}
Case (0x09)
{
If ((ECR1 == 0x01))
{
If ((Arg1 >= 0x03))
{
Return (Package (0x05)
{
0xC350,
Ones,
Ones,
0xC350,
Ones
})
}
}
}
}
}
Return (Buffer (0x01)
{
0x00 // .
})
}
Device (PXSX)
{
Name (_ADR, 0x00) // _ADR: Address
Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (GPRW (0x69, 0x04))
}
}
Method (HPME, 0, Serialized)
{
If (((VDID != 0xFFFFFFFF) && (PMSX == 0x01)))
{
Notify (PXSX, 0x02) // Device Wake
PMSX = 0x01
PSPX = 0x01
}
}
Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (GPRW (0x69, 0x04))
}
}
next prev parent reply other threads:[~2018-12-05 10:40 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-04 11:20 [PATCH] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports Mika Westerberg
2018-12-04 17:55 ` Rafael J. Wysocki
2018-12-04 18:34 ` Mika Westerberg
2018-12-04 20:40 ` Lukas Wunner
2018-12-05 9:20 ` Mika Westerberg
2018-12-05 9:48 ` Lukas Wunner
2018-12-05 10:40 ` Mika Westerberg [this message]
2018-12-05 13:22 ` Lukas Wunner
2018-12-05 13:46 ` Mika Westerberg
2018-12-14 9:24 ` Mika Westerberg
2018-12-17 20:28 ` Bjorn Helgaas
2018-12-18 8:55 ` Mika Westerberg
2018-12-18 20:58 ` Bjorn Helgaas
2018-12-19 13:23 ` Mika Westerberg
2018-12-19 14:45 ` Bjorn Helgaas
2018-12-19 15:15 ` Mika Westerberg
2018-12-19 17:09 ` Lukas Wunner
2018-12-20 10:06 ` Mika Westerberg
2018-12-20 10:23 ` Rafael J. Wysocki
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