From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: linux-pci@vger.kernel.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
Chris Healy <cphealy@gmail.com>,
Lucas Stach <l.stach@pengutronix.de>,
Leonard Crestez <leonard.crestez@nxp.com>,
"A.s. Dong" <aisheng.dong@nxp.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 10/21] PCI: designware: imx6: Share PHY debug register definitions
Date: Thu, 20 Dec 2018 23:27:05 -0800 [thread overview]
Message-ID: <20181221072716.29017-11-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181221072716.29017-1-andrew.smirnov@gmail.com>
Both pcie-designware.c and pci-imx6.c contain custom definitions for
PHY debug registers R0/R1 and on top of that there's already a
definition for R0 in pcie-designware.h. Move all of the definitions to
pcie-designware.h. No functional change intended.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 6 ++----
drivers/pci/controller/dwc/pcie-designware.c | 12 +++---------
drivers/pci/controller/dwc/pcie-designware.h | 3 +++
3 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 74faca11eeae..c0b073cf20c0 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -82,8 +82,6 @@ struct imx6_pcie {
/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
-#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
-#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -706,8 +704,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
err_reset_phy:
dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+ dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
+ dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
imx6_pcie_reset_phy(imx6_pcie);
return ret;
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 67236379c61a..d123ac290b9e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -14,12 +14,6 @@
#include "pcie-designware.h"
-/* PCIe Port Logic registers */
-#define PLR_OFFSET 0x700
-#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
-#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
-
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
{
if (!IS_ALIGNED((uintptr_t)addr, size)) {
@@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
if (pci->ops->link_up)
return pci->ops->link_up(pci);
- val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
- return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
- (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
+ val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
}
void dw_pcie_setup(struct dw_pcie *pci)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9943d8c68335..58735fd01668 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -39,6 +39,9 @@
#define PCIE_PORT_DEBUG0 0x728
#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
#define PORT_LOGIC_LTSSM_STATE_L0 0x11
+#define PCIE_PORT_DEBUG1 0x72C
+#define PCIE_PORT_DEBUG1_LINK_UP (0x1 << 4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING (0x1 << 29)
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
--
2.19.1
next prev parent reply other threads:[~2018-12-21 7:28 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-21 7:26 [PATCH 00/21] i.MX6, DesignWare PCI improvements Andrey Smirnov
2018-12-21 7:26 ` [PATCH 01/21] PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock() Andrey Smirnov
2018-12-21 7:26 ` [PATCH 02/21] PCI: imx6: Remove redundant debug tracing Andrey Smirnov
2018-12-21 7:26 ` [PATCH 03/21] PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() Andrey Smirnov
2018-12-21 7:26 ` [PATCH 04/21] PCI: imx6: Remove duplicate macro definitions Andrey Smirnov
2018-12-21 7:27 ` [PATCH 05/21] PCI: imx6: Remove PCIE_PL_PFLR_* constants Andrey Smirnov
2018-12-21 7:27 ` [PATCH 06/21] PCI: imx6: Remove PCIE_PHY_RX_ASIC_OUT* constants Andrey Smirnov
2018-12-21 7:27 ` [PATCH 07/21] PCI: designware: Make use of IS_ALIGNED() Andrey Smirnov
2019-01-02 9:33 ` Gustavo Pimentel
2019-01-04 18:37 ` Joe Perches
2019-01-04 18:52 ` Andrey Smirnov
2018-12-21 7:27 ` [PATCH 08/21] PCI: designware: Share code for dw_pcie_rd/wr_other_conf() Andrey Smirnov
2019-01-02 10:21 ` Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 09/21] PCI: imx6: Drop imx6_pcie_link_up() Andrey Smirnov
2018-12-21 18:55 ` Trent Piepho
2018-12-22 0:39 ` Andrey Smirnov
2018-12-21 7:27 ` Andrey Smirnov [this message]
2018-12-21 7:27 ` [PATCH 11/21] PCI: designware: Make use of BIT() in constant definitions Andrey Smirnov
2018-12-26 15:14 ` Gustavo Pimentel
2019-01-02 18:28 ` Andrey Smirnov
2019-01-02 18:31 ` Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 12/21] PCI: imx6: " Andrey Smirnov
2018-12-21 7:27 ` [PATCH 13/21] PCI: imx6: Simplify bit operations in PHY functions Andrey Smirnov
2018-12-21 7:27 ` [PATCH 14/21] PCI: imx6: Simplify pcie_phy_poll_ack() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 15/21] PCI: imx6: Restrict PHY register data to 16-bit Andrey Smirnov
2018-12-21 7:27 ` [PATCH 16/21] PCI: imx6: Pass data to dw_pcie_writel_dbi() directly Andrey Smirnov
2018-12-21 7:27 ` [PATCH 17/21] PCI: imx6: Use common mask in imx6_pcie_reset_phy() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 18/21] PCI: imx6: Simplify bit operations in imx6_setup_phy_mpll() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 19/21] PCI: imx6: Remove magic numbers from imx6_pcie_establish_link() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 20/21] PCI: designware: Make use of GENMASK/FIELD_PREP Andrey Smirnov
2018-12-26 15:07 ` Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 21/21] PCI: designware: Remove superfluous shifting in definitions Andrey Smirnov
2018-12-26 14:49 ` Gustavo Pimentel
2018-12-26 15:26 ` [PATCH 00/21] i.MX6, DesignWare PCI improvements Gustavo Pimentel
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