From: Bjorn Helgaas <helgaas@kernel.org>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
Kedar A Dongre <kedar.a.dongre@intel.com>,
Lukas Wunner <lukas@wunner.de>, Peter Wu <peter@lekensteyn.nl>,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v4] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports
Date: Thu, 7 Feb 2019 18:27:31 -0600 [thread overview]
Message-ID: <20190208002731.GS7268@google.com> (raw)
In-Reply-To: <20190131163856.50260-1-mika.westerberg@linux.intel.com>
On Thu, Jan 31, 2019 at 07:38:56PM +0300, Mika Westerberg wrote:
> Gigabyte X299 DESIGNARE EX motherboard has one PCIe root port that is
> connected to an Alpine Ridge Thunderbolt controller. This port has slot
> implemented bit set in the config space but other than that it is not
> hotplug capable in the sense we are expecting in Linux (it has
> dev->is_hotplug_bridge set to 0):
>
> 00:1c.4 PCI bridge: Intel Corporation 200 Series PCH PCI Express Root Port #5
> Bus: primary=00, secondary=05, subordinate=46, sec-latency=0
> Memory behind bridge: 78000000-8fffffff [size=384M]
> Prefetchable memory behind bridge: 00003800f8000000-00003800ffffffff [size=128M]
> ...
> Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
> ...
> SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
> Slot #8, PowerLimit 25.000W; Interlock- NoCompl+
> SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
> Changed: MRL- PresDet+ LinkState+
>
> This system is using ACPI based hotplug to notify the OS that it needs
> to rescan the PCI bus (ACPI hotplug).
>
> If there is nothing connected in any of the Thunderbolt ports the root
> port will not have any runtime PM active children and is thus
> automatically runtime suspended pretty soon after boot by PCI PM core.
> Now, when a device is connected the BIOS SMI handler responsible for
> enumerating newly added devices is not able to find anything because the
> port is in D3.
>
> Prevent this from happening by blacklisting PCI power management of this
> particular Gigabyte system.
Since this is one of those issues we seem to have to discover
experimentally, I'd like to include a URL here to a kernel.org
bugzilla that has a dmesg log, "lspci -vvvnn" output, an acpidump, and
anything else that might be useful to extend or generalize this in the
future. Maybe dmidecode output, too?
If somebody creates the bugzilla, I can add the URL; no need to repost
just for that.
> Reported-by: Kedar A Dongre <kedar.a.dongre@intel.com>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> Changes from v3:
>
> * Added #ifdef CONFIG_X86/#endif over DMI entry as suggested by Lukas.
>
> v3: https://patchwork.kernel.org/patch/10778957/
> v2: https://patchwork.kernel.org/patch/10750549/
> v1: https://patchwork.kernel.org/patch/10711553/
>
> drivers/pci/pci.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index c25acace7d91..7f5385badc1b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -2501,6 +2501,25 @@ void pci_config_pm_runtime_put(struct pci_dev *pdev)
> pm_runtime_put_sync(parent);
> }
>
> +static const struct dmi_system_id bridge_d3_blacklist[] = {
> +#ifdef CONFIG_X86
> + {
> + /*
> + * Gigabyte X299 root port is not marked as hotplug
> + * capable which allows Linux to power manage it.
> + * However, this confuses the BIOS SMI handler so don't
> + * power manage root ports on that system.
> + */
> + .ident = "X299 DESIGNARE EX-CF",
> + .matches = {
> + DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
> + DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
> + },
> + },
> +#endif
> + { }
> +};
> +
> /**
> * pci_bridge_d3_possible - Is it possible to put the bridge into D3
> * @bridge: Bridge to check
> @@ -2546,6 +2565,9 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
> if (bridge->is_hotplug_bridge)
> return false;
>
> + if (dmi_check_system(bridge_d3_blacklist))
> + return false;
> +
> /*
> * It should be safe to put PCIe ports from 2015 or newer
> * to D3.
> --
> 2.20.1
>
next prev parent reply other threads:[~2019-02-08 0:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 16:38 [PATCH v4] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports Mika Westerberg
2019-02-08 0:27 ` Bjorn Helgaas [this message]
2019-02-11 10:27 ` Mika Westerberg
2019-02-11 14:49 ` Bjorn Helgaas
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