* [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
@ 2019-03-12 9:38 Z.q. Hou
0 siblings, 0 replies; 5+ messages in thread
From: Z.q. Hou @ 2019-03-12 9:38 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
lorenzo.pieralisi, catalin.marinas, will.deacon
Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V4:
- no change
.../bindings/pci/layerscape-pci-gen4.txt | 52 +++++++++++++++++++
MAINTAINERS | 8 +++
2 files changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
new file mode 100644
index 000000000000..b40fb5d15d3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
@@ -0,0 +1,52 @@
+NXP Layerscape PCIe Gen4 controller
+
+This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
+the common properties defined in mobiveil-pcie.txt.
+
+Required properties:
+- compatible: should contain the platform identifier such as:
+ "fsl,lx2160a-pcie"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+ "csr_axi_slave": Bridge config registers
+ "config_axi_slave": PCIe controller registers
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+- interrupt-names: It could include the following entries:
+ "intr": The interrupt that is asserted for controller interrupts
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
+ of the data transferred from/to the IP block. This can avoid the software
+ cache flush/invalid actions, and improve the performance significantly.
+- msi-parent : See the generic MSI binding described in
+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+Example:
+
+ pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 1013e74b14f2..2d18c7213991 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11835,6 +11835,14 @@ L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: drivers/pci/controller/dwc/*layerscape*
+PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
+M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+L: linux-pci@vger.kernel.org
+L: linux-arm-kernel@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
+F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c
+
PCI DRIVER FOR GENERIC OF HOSTS
M: Will Deacon <will.deacon@arm.com>
L: linux-pci@vger.kernel.org
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-03-11 22:11 ` Rob Herring
@ 2019-03-12 9:42 ` Z.q. Hou
1 sibling, 0 replies; 5+ messages in thread
From: Z.q. Hou @ 2019-03-12 9:42 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
lorenzo.pieralisi, catalin.marinas, will.deacon
Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao
Hi All,
Please ignore this, has re-sent it adding lost Reviewed-by tag.
Thanks,
Zhiqiang
> -----Original Message-----
> From: Z.q. Hou
> Sent: 2019年3月11日 17:33
> To: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q. Hou
> <zhiqiang.hou@nxp.com>
> Subject: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe
> Gen4 controller
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
> - no change
>
> .../bindings/pci/layerscape-pci-gen4.txt | 52 +++++++++++++++++++
> MAINTAINERS | 8 +++
> 2 files changed, 60 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> new file mode 100644
> index 000000000000..b40fb5d15d3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> @@ -0,0 +1,52 @@
> +NXP Layerscape PCIe Gen4 controller
> +
> +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits
> +all the common properties defined in mobiveil-pcie.txt.
> +
> +Required properties:
> +- compatible: should contain the platform identifier such as:
> + "fsl,lx2160a-pcie"
> +- reg: base addresses and lengths of the PCIe controller register blocks.
> + "csr_axi_slave": Bridge config registers
> + "config_axi_slave": PCIe controller registers
> +- interrupts: A list of interrupt outputs of the controller. Must
> +contain an
> + entry for each entry in the interrupt-names property.
> +- interrupt-names: It could include the following entries:
> + "intr": The interrupt that is asserted for controller interrupts
> + "aer": Asserted for aer interrupt when chip support the aer interrupt with
> + none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
> + "pme": Asserted for pme interrupt when chip support the pme interrupt
> with
> + none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
> +- dma-coherent: Indicates that the hardware IP block can ensure the
> +coherency
> + of the data transferred from/to the IP block. This can avoid the
> +software
> + cache flush/invalid actions, and improve the performance significantly.
> +- msi-parent : See the generic MSI binding described in
> + Documentation/devicetree/bindings/interrupt-controller/msi.txt.
> +
> +Example:
> +
> + pcie@3400000 {
> + compatible = "fsl,lx2160a-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers
> */
> + 0x80 0x00000000 0x0 0x00001000>; /* configuration space
> */
> + reg-names = "csr_axi_slave", "config_axi_slave";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER
> interrupt */
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt
> */
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller
> interrupt */
> + interrupt-names = "aer", "pme", "intr";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + apio-wins = <8>;
> + ppio-wins = <8>;
> + dma-coherent;
> + bus-range = <0x0 0xff>;
> + msi-parent = <&its>;
> + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0
> 0x40000000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 2 &gic 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 3 &gic 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 4 &gic 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1013e74b14f2..2d18c7213991 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11835,6 +11835,14 @@ L: linux-arm-kernel@lists.infradead.org
> S: Maintained
> F: drivers/pci/controller/dwc/*layerscape*
>
> +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
> +M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> +L: linux-pci@vger.kernel.org
> +L: linux-arm-kernel@lists.infradead.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> +F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c
> +
> PCI DRIVER FOR GENERIC OF HOSTS
> M: Will Deacon <will.deacon@arm.com>
> L: linux-pci@vger.kernel.org
> --
> 2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
2019-03-11 22:11 ` Rob Herring
@ 2019-03-12 3:17 ` Z.q. Hou
0 siblings, 0 replies; 5+ messages in thread
From: Z.q. Hou @ 2019-03-12 3:17 UTC (permalink / raw)
To: Rob Herring
Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
lorenzo.pieralisi, catalin.marinas, will.deacon, Mingkai Hu,
M.h. Lian, Xiaowei Bao
Hi Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: 2019年3月12日 6:12
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>; Z.q. Hou <zhiqiang.hou@nxp.com>
> Subject: Re: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe
> Gen4 controller
>
> On Mon, 11 Mar 2019 09:33:05 +0000, "Z.q. Hou" wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V4:
> > - no change
> >
> > .../bindings/pci/layerscape-pci-gen4.txt | 52
> +++++++++++++++++++
> > MAINTAINERS | 8 +++
> > 2 files changed, 60 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> >
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
>
> If a tag was not added on purpose, please state why and what changed.
Sorry, I missed your Reviewed-by tag in this patch, will re-send this patch adding the lost tag.
Thanks,
Zhiqiang
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
@ 2019-03-11 22:11 ` Rob Herring
2019-03-12 3:17 ` Z.q. Hou
2019-03-12 9:42 ` Z.q. Hou
1 sibling, 1 reply; 5+ messages in thread
From: Rob Herring @ 2019-03-11 22:11 UTC (permalink / raw)
To: Z.q. Hou
Cc: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
lorenzo.pieralisi, catalin.marinas, will.deacon, Mingkai Hu,
M.h. Lian, Xiaowei Bao, Z.q. Hou
On Mon, 11 Mar 2019 09:33:05 +0000, "Z.q. Hou" wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
> - no change
>
> .../bindings/pci/layerscape-pci-gen4.txt | 52 +++++++++++++++++++
> MAINTAINERS | 8 +++
> 2 files changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
2019-03-11 9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
@ 2019-03-11 9:33 ` Z.q. Hou
2019-03-11 22:11 ` Rob Herring
2019-03-12 9:42 ` Z.q. Hou
0 siblings, 2 replies; 5+ messages in thread
From: Z.q. Hou @ 2019-03-11 9:33 UTC (permalink / raw)
To: linux-pci, linux-arm-kernel, devicetree, linux-kernel, bhelgaas,
robh+dt, mark.rutland, l.subrahmanya, shawnguo, Leo Li,
lorenzo.pieralisi, catalin.marinas, will.deacon
Cc: Mingkai Hu, M.h. Lian, Xiaowei Bao, Z.q. Hou
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V4:
- no change
.../bindings/pci/layerscape-pci-gen4.txt | 52 +++++++++++++++++++
MAINTAINERS | 8 +++
2 files changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
new file mode 100644
index 000000000000..b40fb5d15d3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
@@ -0,0 +1,52 @@
+NXP Layerscape PCIe Gen4 controller
+
+This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
+the common properties defined in mobiveil-pcie.txt.
+
+Required properties:
+- compatible: should contain the platform identifier such as:
+ "fsl,lx2160a-pcie"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+ "csr_axi_slave": Bridge config registers
+ "config_axi_slave": PCIe controller registers
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+ entry for each entry in the interrupt-names property.
+- interrupt-names: It could include the following entries:
+ "intr": The interrupt that is asserted for controller interrupts
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
+- dma-coherent: Indicates that the hardware IP block can ensure the coherency
+ of the data transferred from/to the IP block. This can avoid the software
+ cache flush/invalid actions, and improve the performance significantly.
+- msi-parent : See the generic MSI binding described in
+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+Example:
+
+ pcie@3400000 {
+ compatible = "fsl,lx2160a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+ reg-names = "csr_axi_slave", "config_axi_slave";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "aer", "pme", "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ apio-wins = <8>;
+ ppio-wins = <8>;
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ msi-parent = <&its>;
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 1013e74b14f2..2d18c7213991 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11835,6 +11835,14 @@ L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: drivers/pci/controller/dwc/*layerscape*
+PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
+M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+L: linux-pci@vger.kernel.org
+L: linux-arm-kernel@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
+F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c
+
PCI DRIVER FOR GENERIC OF HOSTS
M: Will Deacon <will.deacon@arm.com>
L: linux-pci@vger.kernel.org
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-03-12 9:42 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2019-03-12 9:38 [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
-- strict thread matches above, loose matches on Subject: below --
2019-03-11 9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-03-11 22:11 ` Rob Herring
2019-03-12 3:17 ` Z.q. Hou
2019-03-12 9:42 ` Z.q. Hou
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