From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com,
kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
mperttunen@nvidia.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V5 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
Date: Fri, 3 May 2019 13:26:37 +0200 [thread overview]
Message-ID: <20190503112637.GF32400@ulmo> (raw)
In-Reply-To: <20190424052004.6270-13-vidyas@nvidia.com>
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On Wed, Apr 24, 2019 at 10:50:00AM +0530, Vidya Sagar wrote:
> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
> The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
> grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
> and NVIDIA High Speed (NVHS-8 P2Us) respectively.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> Changes since [v4]:
> * None
>
> Changes since [v3]:
> * None
>
> Changes since [v2]:
> * Included 'hsio' or 'nvhs' in P2U node's label names to reflect which brick
> they belong to
> * Removed leading zeros in unit address
>
> Changes since [v1]:
> * Flattened all P2U nodes by removing 'hsio-p2u' and 'nvhs-p2u' super nodes
> * Changed P2U nodes compatible string from 'nvidia,tegra194-phy-p2u' to 'nvidia,tegra194-p2u'
> * Changed reg-name from 'base' to 'ctl'
> * Updated all PCIe nodes according to the changes made to DT documentation file
>
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 449 +++++++++++++++++++++++
> 1 file changed, 449 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index c77ca211fa8f..dc433b446ff5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
[...]
> + pcie@14180000 {
[...]
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
> + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
> + 0x82000000 0x0 0x40000000 0x1B 0x40000000 0x0 0xC0000000>; /* non-prefetchable memory (3GB) */
Please be consistent in the capitalization of hexadecimal numbers. You
use lowercase hexdigits in one place and upprecase in others. Just stick
to one (preferably lowercase since that's already used elsewhere in this
file).
> + };
> +
> + pcie@14100000 {
Also, entries should be sorted by unit-address, so controller 0 above
needs to go further down.
Thierry
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next prev parent reply other threads:[~2019-05-03 11:26 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 5:19 [PATCH V5 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-05-03 11:01 ` Thierry Reding
2019-05-07 7:10 ` Vidya Sagar
2019-05-07 7:51 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-05-03 11:07 ` Thierry Reding
2019-05-10 6:21 ` Vidya Sagar
2019-05-10 16:46 ` Bjorn Helgaas
2019-05-10 17:50 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-03 11:13 ` Thierry Reding
2019-05-07 7:49 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-24 8:13 ` Gustavo Pimentel
2019-05-07 8:04 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-26 14:32 ` Rob Herring
2019-05-07 8:25 ` Vidya Sagar
2019-05-13 15:15 ` Rob Herring
2019-05-14 5:29 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-26 15:22 ` Rob Herring
2019-05-07 8:31 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-26 15:43 ` Rob Herring
2019-05-07 9:20 ` Vidya Sagar
2019-05-13 15:20 ` Rob Herring
2019-05-14 6:25 ` Vidya Sagar
2019-05-03 11:19 ` Thierry Reding
2019-05-07 9:26 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-26 15:45 ` Rob Herring
2019-04-26 16:07 ` Thierry Reding
2019-04-26 18:05 ` Rob Herring
2019-05-07 9:57 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-03 11:26 ` Thierry Reding [this message]
2019-05-07 10:10 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-03 11:27 ` Thierry Reding
2019-05-07 10:11 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-03 11:35 ` Thierry Reding
2019-05-07 10:25 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-03 13:08 ` Thierry Reding
2019-05-07 13:54 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
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