From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<jonathanh@nvidia.com>, <kishon@ti.com>,
<catalin.marinas@arm.com>, <will.deacon@arm.com>,
<jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
<mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
<mmaddireddy@nvidia.com>, <sagar.tv@gmail.com>
Subject: Re: [PATCH V5 04/16] PCI: dwc: Perform dbi regs write lock towards the end
Date: Tue, 7 May 2019 13:19:32 +0530 [thread overview]
Message-ID: <2544621a-4c88-3f3e-786c-7ee8103e132d@nvidia.com> (raw)
In-Reply-To: <20190503111303.GD32400@ulmo>
On 5/3/2019 4:43 PM, Thierry Reding wrote:
> On Wed, Apr 24, 2019 at 10:49:52AM +0530, Vidya Sagar wrote:
>> Remove multiple write enable and disable sequences of dbi registers as
>> Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
>> DBI write-lock enable bit thereby not allowing any further writes to BAR-0
>> register in config space to take place. Hence disabling write permission
>> only towards the end.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> Changes since [v4]:
>> * None
>>
>> Changes since [v3]:
>> * None
>>
>> Changes since [v2]:
>> * None
>>
>> Changes since [v1]:
>> * None
>>
>> drivers/pci/controller/dwc/pcie-designware-host.c | 3 ---
>> 1 file changed, 3 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
>> index 36fd3f5b48f6..e5e3571dd2fe 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
>> @@ -654,7 +654,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>> val &= 0xffff00ff;
>> val |= 0x00000100;
>> dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
>> - dw_pcie_dbi_ro_wr_dis(pci);
>>
>> /* Setup bus numbers */
>> val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
>> @@ -686,8 +685,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>>
>> dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>>
>> - /* Enable write permission for the DBI read-only register */
>> - dw_pcie_dbi_ro_wr_en(pci);
>> /* Program correct class for RC */
>> dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
>> /* Better disable write permission right after the update */
>
> Perhaps make this explicit by moving the write enable call to the
> beginning of the function and the write disable call to the end?
>
> Currently it's pretty difficult to see where it's being disabled. Also,
> that would make it more resilient against instantiations that require a
> different register to be programmed with writes enabled.
Agree. I'll move enabling write to beginning of this function and disabling
to the end in the next patch series.
>
> Thierry
>
next prev parent reply other threads:[~2019-05-07 7:49 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-24 5:19 [PATCH V5 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 01/16] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 02/16] PCI/PME: Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs Vidya Sagar
2019-05-03 11:01 ` Thierry Reding
2019-05-07 7:10 ` Vidya Sagar
2019-05-07 7:51 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-05-03 11:07 ` Thierry Reding
2019-05-10 6:21 ` Vidya Sagar
2019-05-10 16:46 ` Bjorn Helgaas
2019-05-10 17:50 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-05-03 11:13 ` Thierry Reding
2019-05-07 7:49 ` Vidya Sagar [this message]
2019-04-24 5:19 ` [PATCH V5 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-24 8:13 ` Gustavo Pimentel
2019-05-07 8:04 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 06/16] PCI: dwc: Add ext " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-26 14:32 ` Rob Herring
2019-05-07 8:25 ` Vidya Sagar
2019-05-13 15:15 ` Rob Herring
2019-05-14 5:29 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-26 15:22 ` Rob Herring
2019-05-07 8:31 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-26 15:43 ` Rob Herring
2019-05-07 9:20 ` Vidya Sagar
2019-05-13 15:20 ` Rob Herring
2019-05-14 6:25 ` Vidya Sagar
2019-05-03 11:19 ` Thierry Reding
2019-05-07 9:26 ` Vidya Sagar
2019-04-24 5:19 ` [PATCH V5 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-26 15:45 ` Rob Herring
2019-04-26 16:07 ` Thierry Reding
2019-04-26 18:05 ` Rob Herring
2019-05-07 9:57 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-05-03 11:26 ` Thierry Reding
2019-05-07 10:10 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-05-03 11:27 ` Thierry Reding
2019-05-07 10:11 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-05-03 11:35 ` Thierry Reding
2019-05-07 10:25 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-05-03 13:08 ` Thierry Reding
2019-05-07 13:54 ` Vidya Sagar
2019-04-24 5:20 ` [PATCH V5 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
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