Fwd: [Bug 203485] New: PCI can't map correct memory resource if the BAR is 64-bit and then leads to system hang during booting up

Fwd: [Bug 203485] New: PCI can't map correct memory resource if the BAR is 64-bit and then leads to system hang during booting up

[Bjorn Helgaas]

I should have forwarded this to the list earlier.  Maybe somebody
wants to work on this?

I *think* the problem is:

  - BIOS sets MTRR for 0x40_00000000-0x5f_ffffffff to be write-combining (WC)
  - That covers part of this PCI aperture: root bus resource [mem
0x40_00000000-0x7f_ffffffff window]
  - That aperture includes a frame buffer: pci 0000:00:02.0: reg 0x18:
[mem 0x40_00000000-0x40_0fffffff 64bit pref]
  - Linux assigned an LPSS BAR to the WC area: pci 0000:00:15.0: BAR
0: assigned [mem 0x40_10000000-0x40_10000fff 64bit]
  - The LPSS device doesn't work if MMIO accesses to it are combined via WC

I'm not an x86/MTRR/PAT expert, but I think we should be able to make
this work correctly by changing that MTRR from WC to UC (I don't know
if there are BIOS/OS interface implications with this), or maybe using
PAT to override the MTRR WC setting to be UC for part or all of that
aperture.  The frame buffer driver should be smart enough to request
WC if it wants it.


---------- Forwarded message ---------
From: <bugzilla-daemon@bugzilla.kernel.org>
Date: Fri, May 3, 2019 at 3:31 AM
Subject: [Bug 203485] New: PCI can't map correct memory resource if
the BAR is 64-bit and then leads to system hang during booting up
To: <bugzilla.pci@gmail.com>


https://bugzilla.kernel.org/show_bug.cgi?id=203485

            Bug ID: 203485
           Summary: PCI can't map correct memory resource if the BAR is
                    64-bit and then leads to system hang during booting up
           Product: Drivers
           Version: 2.5
    Kernel Version: v5.1-rc7
          Hardware: All
                OS: Linux
              Tree: Mainline
            Status: NEW
          Severity: normal
          Priority: P1
         Component: PCI
          Assignee: drivers_pci@kernel-bugs.osdl.org
          Reporter: acelan@gmail.com
        Regression: No

Created attachment 282597
  --> https://bugzilla.kernel.org/attachment.cgi?id=282597&action=edit
dmesg.log

This issue has been found on loading intel-lpss-pci driver, the pdev->resource
passing to its probe function is not correct. And it leads to system hangs
while loading the driver.

This is the memory addresses driver got, the start and end are more like the
region declared in BAR

[    0.718591] pci 0000:00:15.0: BAR 0: assigned [mem 0x4010000000-0x4010000fff
64bit]
[    0.718613] pci 0000:00:15.1: BAR 0: assigned [mem 0x4010001000-0x4010001fff
64bit]
[    0.718626] pci 0000:00:1d.0: BAR 13: assigned [io  0x4000-0x6fff]
[    0.718634] pci 0000:00:1e.0: BAR 0: assigned [mem 0x4010002000-0x4010002fff
64bit]

[  154.417550] [/home/acelan/linux/drivers/mfd/intel-lpss-pci.c:31]
intel_lpss_pci_probe(): 0000:00:15.0 - mem = 0x0000000047753398, mem->start =
0x0000000010000000, mem->end = 0x0000000010000FFF
[  154.417571] [/home/acelan/linux/drivers/mfd/intel-lpss-pci.c:31]
intel_lpss_pci_probe(): 0000:00:15.1 - mem = 0x0000000047754398, mem->start =
0x0000000010001000, mem->end = 0x0000000010001FFF
[  154.417587] [/home/acelan/linux/drivers/mfd/intel-lpss-pci.c:31]
intel_lpss_pci_probe(): 0000:00:1e.0 - mem = 0x000000004775A398, mem->start =
0x0000000010002000, mem->end = 0x0000000010002FFF

Below is the correct one I copy from 32-Bit BAR
[    3.511100] [/home/acelan/bionic/drivers/mfd/intel-lpss-pci.c:47]
intel_lpss_pci_probe(): 0000:00:15.0 - mem = 0x00000000AB282380, mem->start =
0x00000000ED137000, mem->end = 0x00000000ED137FFF

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Re: Fwd: [Bug 203485] New: PCI can't map correct memory resource if the BAR is 64-bit and then leads to system hang during booting up

[Andy Shevchenko]

On Wed, May 15, 2019 at 02:26:13PM -0500, Bjorn Helgaas wrote:
> I should have forwarded this to the list earlier.  Maybe somebody
> wants to work on this?
> 
> I *think* the problem is:
> 
>   - BIOS sets MTRR for 0x40_00000000-0x5f_ffffffff to be write-combining (WC)
>   - That covers part of this PCI aperture: root bus resource [mem
> 0x40_00000000-0x7f_ffffffff window]
>   - That aperture includes a frame buffer: pci 0000:00:02.0: reg 0x18:
> [mem 0x40_00000000-0x40_0fffffff 64bit pref]
>   - Linux assigned an LPSS BAR to the WC area: pci 0000:00:15.0: BAR
> 0: assigned [mem 0x40_10000000-0x40_10000fff 64bit]
>   - The LPSS device doesn't work if MMIO accesses to it are combined via WC
> 
> I'm not an x86/MTRR/PAT expert, but I think we should be able to make
> this work correctly by changing that MTRR from WC to UC (I don't know
> if there are BIOS/OS interface implications with this), or maybe using
> PAT to override the MTRR WC setting to be UC for part or all of that
> aperture.  The frame buffer driver should be smart enough to request
> WC if it wants it.

The window for the PCI resources, provided by PCI Root Bridge, may be split to
many parts as described by _CRS in ACPI, and BIOS should be consistent in
providing both.

I believe there is no issue with Linux in current state. Be "smart" here might
give a downside(s) like reducing coverage to test exactly something as above
BIOS issue.

My 2 cents.

-- 
With Best Regards,
Andy Shevchenko