From: Andrew Murray <andrew.murray@arm.com>
To: Jonathan Chocron <jonnyc@amazon.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
robh+dt@kernel.org, mark.rutland@arm.com, dwmw@amazon.co.uk,
benh@kernel.crashing.org, alisaidi@amazon.com, ronenk@amazon.com,
barakw@amazon.com, talel@amazon.com, hanochu@amazon.com,
hhhawa@amazon.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 7/7] PCI: dwc: Add validation that PCIe core is set to correct mode
Date: Thu, 22 Aug 2019 12:13:16 +0100 [thread overview]
Message-ID: <20190822111315.GN23903@e119886-lin.cambridge.arm.com> (raw)
In-Reply-To: <20190821154745.31834-3-jonnyc@amazon.com>
On Wed, Aug 21, 2019 at 06:47:45PM +0300, Jonathan Chocron wrote:
> Some PCIe controllers can be set to either Host or EP according to some
> early boot FW. To make sure there is no discrepancy (e.g. FW configured
> the port to EP mode while the DT specifies it as a host bridge or vice
> versa), a check has been added for each mode.
>
> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++
> drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 2bf5a35c0570..00e59a134b93 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> int ret;
> u32 reg;
> void *addr;
> + u8 hdr_type;
> unsigned int nbars;
> unsigned int offset;
> struct pci_epc *epc;
> @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return -EINVAL;
> }
>
> + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> + if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
> + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
> + hdr_type);
> + return -EIO;
> + }
> +
> ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
> if (ret < 0) {
> dev_err(dev, "Unable to read *num-ib-windows* property\n");
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f93252d0da5b..d2ca748e4c85 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> struct pci_bus *child;
> struct pci_host_bridge *bridge;
> struct resource *cfg_res;
> + u8 hdr_type;
> int ret;
>
> raw_spin_lock_init(&pci->pp.lock);
> @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
> }
>
> + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
Do we know if it's always safe to read these registers at this point in time?
Later in dw_pcie_host_init we call pp->ops->host_init - looking at the
implementations of .host_init I can see:
- resets being performed (qcom_ep_reset_assert,
artpec6_pcie_assert_core_reset, imx6_pcie_assert_core_reset)
- changes to config space registers (ks_pcie_init_id, dw_pcie_setup_rc)
including setting PCI_CLASS_DEVICE
- and clocks being enabled (qcom_pcie_init_1_0_0)
I'm not sure if your changes would cause anything to break for these other
controllers (or future controllers) as I couldn't see any other reads to the
config.
Given that we are reading config space should dw_pcie_rd_own_conf be used?
(For example kirin_pcie_rd_own_conf does something special).
Thanks,
Andrew Murray
> + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
> + dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
> + hdr_type);
> + return -EIO;
> + }
> +
> pp->mem_base = pp->mem->start;
>
> if (!pp->va_cfg0_base) {
> --
> 2.17.1
>
next prev parent reply other threads:[~2019-08-22 11:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 15:35 [PATCH v4 0/7] Amazon's Annapurna Labs DT-based PCIe host controller driver Jonathan Chocron
2019-08-21 15:35 ` [PATCH v4 1/7] PCI: Add Amazon's Annapurna Labs vendor ID Jonathan Chocron
2019-08-21 15:35 ` [PATCH v4 2/7] PCI: Add ACS quirk for Amazon Annapurna Labs root ports Jonathan Chocron
2019-08-22 8:31 ` Andrew Murray
2019-09-04 13:33 ` Chocron, Jonathan
2019-08-21 15:35 ` [PATCH v4 3/7] PCI/VPD: Add VPD release quirk for Amazon's Annapurna Labs Root Port Jonathan Chocron
2019-08-22 11:41 ` Andrew Murray
2019-08-22 14:36 ` Chocron, Jonathan
2019-08-22 15:07 ` Andrew Murray
2019-09-04 13:36 ` Chocron, Jonathan
2019-09-04 14:08 ` Andrew Murray
2019-08-22 15:08 ` Andrew Murray
2019-08-21 15:35 ` [PATCH v4 4/7] PCI: Add quirk to disable MSI-X support " Jonathan Chocron
2019-08-22 7:54 ` Andrew Murray
2019-08-21 15:47 ` [PATCH v4 5/7] dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding Jonathan Chocron
2019-08-22 11:15 ` Andrew Murray
2019-08-27 18:53 ` Rob Herring
2019-08-21 15:47 ` [PATCH v4 6/7] PCI: dwc: al: Add support for DW based driver type Jonathan Chocron
2019-08-22 10:00 ` Andrew Murray
2019-08-22 15:23 ` Chocron, Jonathan
2019-08-21 15:47 ` [PATCH v4 7/7] PCI: dwc: Add validation that PCIe core is set to correct mode Jonathan Chocron
2019-08-22 11:13 ` Andrew Murray [this message]
2019-08-22 16:30 ` Chocron, Jonathan
2019-08-27 9:48 ` Andrew Murray
2019-09-04 13:40 ` Chocron, Jonathan
2019-09-02 9:58 ` [PATCH v4 0/7] Amazon's Annapurna Labs DT-based PCIe host controller driver Lorenzo Pieralisi
2019-09-04 13:41 ` Chocron, Jonathan
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