From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: "marek.vasut+renesas@gmail.com" <marek.vasut+renesas@gmail.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v4 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence
Date: Tue, 12 Nov 2019 10:27:06 +0000 [thread overview]
Message-ID: <20191112102706.GA12685@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <TYAPR01MB4544F0F0BCAC5116731D15A9D8770@TYAPR01MB4544.jpnprd01.prod.outlook.com>
[removed CC stable]
On Tue, Nov 12, 2019 at 01:48:03AM +0000, Yoshihiro Shimoda wrote:
[...]
> I'm sorry. I think I should not drop a sentence "because the bit 0 is
> set to 1 on reset" which has the reverted patch from this version. Also,
> the note seems to be difficult to understand. So, I'll rewrite this log
> like below. Is it acceptable?
>
> ---
> According to the R-Car Gen2/3 manual,
Is this a publicly available manual ? If yes we provide a link, if
not I will reword the sentence below.
> "Be sure to write the initial value (= H'80FF 0000) to MACCTLR before
> enabling PCIETCTLR.CFINIT" because the bit 0 of MACCTLR is set to 1 on
> reset. To avoid unexpected behaviors, this patch fixes it.
>
> Note that the SPCHG bit (bit 24) of MACCTLR register description said
> "Only writing 1 is valid and writing 0 is invalid", but this "invalid"
> means "ignored", not "prohibited". So, even if the driver writes
> the SPCHG to 0, there is no problem.
I know understand it, let me know if we can add a link to a manual
(plus section/paragraph, etc.), I will rewrite the commit log
accordingly.
Thanks,
Lorenzo
> ---
>
> Best regards,
> Yoshihiro Shimoda
>
next prev parent reply other threads:[~2019-11-12 10:27 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 10:51 [PATCH v4 0/2] PCI: rcar: Fix missing MACCTLR register setting (take2) Yoshihiro Shimoda
2019-11-05 10:51 ` [PATCH v4 1/2] Revert "PCI: rcar: Fix missing MACCTLR register setting in rcar_pcie_hw_init()" Yoshihiro Shimoda
2019-11-11 14:38 ` Lorenzo Pieralisi
2019-11-12 1:26 ` Yoshihiro Shimoda
2019-11-05 10:51 ` [PATCH v4 2/2] PCI: rcar: Fix missing MACCTLR register setting in initialize sequence Yoshihiro Shimoda
2019-11-11 14:42 ` Lorenzo Pieralisi
2019-11-12 1:48 ` Yoshihiro Shimoda
2019-11-12 10:27 ` Lorenzo Pieralisi [this message]
2019-11-12 10:46 ` Geert Uytterhoeven
2019-11-12 11:25 ` Lorenzo Pieralisi
2019-11-13 1:34 ` Yoshihiro Shimoda
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