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From: Bjorn Helgaas <helgaas@kernel.org>
To: Sean V Kelley <sean.v.kelley@linux.intel.com>
Cc: mj@ucw.cz, linux-pci@vger.kernel.org
Subject: Re: [RFC Patch 1/1] lspci: Add basic decode support for Compute eXpress Link
Date: Wed, 8 Apr 2020 16:47:47 -0500	[thread overview]
Message-ID: <20200408214747.GA129363@google.com> (raw)
In-Reply-To: <1766804A-54D2-4977-975A-9E9F29EFC155@linux.intel.com>

On Wed, Apr 08, 2020 at 02:12:45PM -0700, Sean V Kelley wrote:
> On 8 Apr 2020, at 9:56, Bjorn Helgaas wrote:
> > On Tue, Apr 07, 2020 at 05:09:59PM -0700, Sean V Kelley wrote:

> > > +#define PCI_EVNDR_CXL_ID	0
> > 
> > Unused in this patch.  Is this the DVSEC Vendor ID as described in
> > PCIe r5.0, sec 7.9.6.2?  Is 0 really the ID assigned for CXL?
> 
> It is as described in the PCIe Spec.  The DVSEC ID is set to 0x0 here to
> advertise that this is a Flex Bus feature capability structure. It’s
> assigned in table 58 “PCI Express DVSEC Register Settings for Flex Bus
> Device” of the CXL 1.1 spec.

It sounds like it's the "DVSEC ID" (not the "DVSEC Vendor ID") that is
zero.  That would make sense to me because the "DVSEC ID" is
completely under vendor control.

I would expect the "DVSEC Vendor ID" to be assigned by the PCI-SIG,
and I would be surprised if they assigned zero to CXL.

So I assume you'll eventually #define both IDs here and I won't be
confused any more :)

Thanks for proactively working on this support in lspci!

Bjorn

      reply	other threads:[~2020-04-08 21:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-08  0:09 [RFC Patch 0/1] pciutils: Add basic decode support for CXL Sean V Kelley
2020-04-08  0:09 ` [RFC Patch 1/1] lspci: Add basic decode support for Compute eXpress Link Sean V Kelley
2020-04-08 16:56   ` Bjorn Helgaas
2020-04-08 21:12     ` Sean V Kelley
2020-04-08 21:47       ` Bjorn Helgaas [this message]

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