From: Bjorn Helgaas <helgaas@kernel.org>
To: Sean V Kelley <sean.v.kelley@linux.intel.com>
Cc: mj@ucw.cz, linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 2/2] pciutils: Decode Compute eXpress Link DVSEC
Date: Tue, 14 Apr 2020 15:37:11 -0500 [thread overview]
Message-ID: <20200414203711.GA102808@google.com> (raw)
In-Reply-To: <20200413153526.805776-3-sean.v.kelley@linux.intel.com>
On Mon, Apr 13, 2020 at 08:35:26AM -0700, Sean V Kelley wrote:
> Compute eXpress Link[1] is a new CPU interconnect created with
> workload accelerators in mind. The interconnect relies on PCIe
> electrical and physical interconnect for communication via a Flex Bus
> port which allows designs to choose between providing PCIe or CXL.
>
> This patch introduces basic support for lspci decode of CXL and
> builds upon the existing Designated Vendor-Specific support in
> lspci through identification of a Flex Bus capable Vendor ID.
I don't think this is quite right. Isn't the Flex Bus ID the
"DVSEC ID" (not the "DVSEC Vendor ID")?
> +static int
> +is_flexbus_cap(struct device *d, int where)
> +{
> + u32 hdr;
> + u16 w;
> +
> + if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
> + return 0;
And here, I think we need to check the "DVSEC Vendor ID" first, i.e.,
in the log below, I guess we'd look for the Intel Vendor ID (0x8086).
We can only decode the capability if *both* the DVSEC Vendor ID
(HEADER1) and the DVSEC ID (HEADER2) match.
> + /* Check for Designated Vendor-Specific Flex Bus Capable ID */
> + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2);
> + w = BITS(hdr, 0, 16);
> + if (w == PCI_DVSEC_FLEXBUS_ID)
> + return 1;
> +
> + return 0;
> +}
> +
> static void
> cap_dvsec(struct device *d, int where)
> {
> @@ -947,7 +992,10 @@ show_ext_caps(struct device *d, int type)
> printf("Readiness Time Reporting <?>\n");
> break;
> case PCI_EXT_CAP_ID_DVSEC:
> - cap_dvsec(d, where);
> + if (is_flexbus_cap(d, where))
> + cap_cxl(d, where);
> + else
> + cap_dvsec(d, where);
> break;
> case PCI_EXT_CAP_ID_VF_REBAR:
> printf("VF Resizable BAR <?>\n");
> + Capabilities: [e00 v1] CXL Designated Vendor-Specific:
> + CXLCap: Cache+ IO+ Mem+ Mem HW Init+ HDMCount 1 Viral-
> + CXLCtl: Cache+ IO+ Mem- Cache SF Cov 0 Cache SF Gran 0 Cache Clean- Viral-
> + CXLSta: Viral-
> + Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00
> +e00: 23 00 81 e3 86 80 80 03 00 00 1f 00 03 00 00 00
> +e10: 00 00 00 00 00 00 00 00 00 00 00 00 03 01 00 08
> +e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> +e30: 00 00 00 00 00 00 00 00 03 00 01 00 00 00 00 90
> +e40: 78 56 34 12 00 00 00 00 00 00 00 00 00 00 00 00
next prev parent reply other threads:[~2020-04-14 20:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-13 15:35 [PATCH v4 0/2] pciutils: Add basic decode support for CXL DVSEC Sean V Kelley
2020-04-13 15:35 ` [PATCH v4 1/2] pciutils: Decode available DVSEC details Sean V Kelley
2020-04-13 15:35 ` [PATCH v4 2/2] pciutils: Decode Compute eXpress Link DVSEC Sean V Kelley
2020-04-14 20:37 ` Bjorn Helgaas [this message]
2020-04-14 21:01 ` Sean V Kelley
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